IP Library Granted Patent US 10,762,019
Granted Patent B2
US 10,762,019 · App. 15/647,077 · Granted Sep 1, 2020

Bus sharing scheme

Inventors: Timothy John Williams (Bellevue, WA); David G. Wright (Woodinville, WA); Harold M. Kutz (Edmonds, WA); Eashwar Thiagarajan (Bothell, WA); Warren S. Snyder (Snohomish, WA); Mark E Hastings (Mukilteo, WA)
Assignee: Cypress Semiconductor Corporation
G06F13/4022H03K19/1732
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Quick Facts
Patent No.
US 10,762,019
App. No.
15/647,077
Granted
Sep 1, 2020
Kind
B2
Abstract

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Claims (13)

1. An integrated circuit comprising:

a plurality of configurable components, the plurality of configurable components comprising:

a first set of configurable analog components, and

a second set of configurable digital components;

a routing fabric coupled to the plurality of configurable components, the routing fabric comprising:

a plurality of first analog switches for connection to the first set of configurable analog components, and

a plurality of second digital switches for connection to the second set of configurable digital components;

a plurality of GPIO pads coupled to the routing fabric, the routing fabric for coupling at least two of the configurable components and at least one of the plurality of GPIO pads; and

a control circuit to define a configuration of the routing fabric.

2. The integrated circuit of claim 1 , wherein the at least two of the configurable components comprises at least one configurable digital component and at least one configurable analog component.

3. The integrated circuit of claim 2 , wherein the at least one digital component and the at least one analog component are programmable.

4. The integrated circuit of claim 1 , further comprising at least one fixed-function component.

5. The integrated circuit of claim 1 , further comprising a central processing unit coupled to the routing fabric.

Assignments (5)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
PATENT SECURITY AGREEMENT Recorded Jun 21, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 046402/0277 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2017
From: WILLIAMS, TIMOTHY; WRIGHT, DAVID G.; KUTZ, HAROLD; THIAGARAJAN, EASHWAR; SNYDER, WARREN; HASTINGS, MARK E.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 043855/0306 →
Continuity (5)
Continuation 14540238 · Nov 13, 2014
Continuation 13893201 · May 13, 2013
Continuation 12496579 · Jul 1, 2009
Provisional Application 61077466 · Jul 1, 2008
Related Publication 20170371824A1 · Dec 28, 2017