IP Library Patent Application 15647631
Patent Application
App. No. 15/647,631

Low Parasitic Surface Mount Circuit Over Wirebond IC

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Quick Facts
Patent No.
US None
App. No.
15/647,631
Abstract

A semiconductor device has an interposer and a surface mount technology (SMT) component disposed on the interposer. The interposer is disposed on an active surface of a semiconductor die. The semiconductor die is disposed on a substrate. A first wire bond connection is formed between the interposer and semiconductor die. A second wire bond connection is formed between the interposer and substrate. A third wire bond connection is formed between the substrate and semiconductor die. An encapsulant is deposited over the substrate, semiconductor die, interposer, and SMT component. In one embodiment, the substrate is a quad flat non-leaded substrate. In another embodiment, the substrate is a land-grid array substrate, ball-grid array substrate, or leadframe.

Claims (57)

1 . A method of making a semiconductor device, comprising:

providing an interposer;

disposing a surface mount component over the interposer;

providing a semiconductor die;

disposing the interposer over the semiconductor die; and

forming a first bond wire between the interposer and semiconductor die.

2 . The method of claim 1 , further including:

providing a package substrate; and

disposing the semiconductor die over the package substrate.

3 . The method of claim 2 , further including forming a second bond wire between the package substrate and the interposer.

4 . The method of claim 1 , further including:

forming a transmission line over the interposer, wherein the first bond wire is coupled to a first end of the transmission line; and

forming a second bond wire coupled to a second end of the transmission line.

5 . The method of claim 4 , further including coupling the transmission line and surface mount component in series between the first bond wire and second bond wire.

6 . The method of claim 4 , further including:

coupling the first bond wire to a first contact pad of the semiconductor die; and

coupling the second bond wire to a second contact pad of the semiconductor die, wherein the first bond pad and second bond pad are adjacent to opposites edges of the interposer.

7 . A method of making a semiconductor device, comprising:

providing an interposer;

disposing a surface mount component on the interposer;

providing a semiconductor die; and

disposing the interposer on an active surface of the semiconductor die.

8 . The method of claim 7 , further including forming a transmission line over the interposer.

9 . The method of claim 8 , further including:

forming a first bond wire coupled from the semiconductor die to a first end of the transmission line; and

forming a second bond wire coupled from the semiconductor die to a second end of the transmission line.

10 . The method of claim 7 , further including:

providing a substrate; and

disposing the semiconductor die over the substrate.

11 . The method of claim 10 , further including forming a wire bond connection between the interposer and substrate.

12 . The method of claim 10 , further including depositing an encapsulant over the substrate, semiconductor die, and interposer.

13 . The method of claim 10 , wherein the substrate is a quad flat non-leaded substrate.

14 . A semiconductor device, comprising:

a semiconductor die;

an interposer disposed on an active surface of the semiconductor die;

a surface mount component disposed on the interposer; and

a first bond wire coupled between the interposer and semiconductor die.

15 . The semiconductor device of claim 14 , wherein the semiconductor die includes a ring of contact pads surrounding the interposer.

16 . The semiconductor device of claim 14 , further including a transmission line formed on the interposer, wherein the first bond wire is coupled to a first end of the transmission line.

17 . The semiconductor device of claim 16 , further including:

a substrate disposed over the semiconductor die opposite the interposer; and

a second bond wire coupled between the substrate and a second end of the transmission line.

18 . The semiconductor device of claim 16 , wherein the surface mount component is a capacitor coupled in series with the transmission line.

19 . The semiconductor device of claim 14 , further including an active circuit component disposed on the interposer.

20 . A semiconductor device, comprising:

a semiconductor die;

an interposer disposed on an active surface of the semiconductor die; and

a surface mount component disposed on a surface of the interposer.

21 . The semiconductor device of claim 20 , further including:

a first bond wire coupled between the interposer and the semiconductor die; and

a second bond wire coupled between the interposer and the semiconductor die, wherein surface mount component is coupled between the first bond wire and second bond wire.

22 . The semiconductor device of claim 21 , further including a transmission line formed over the interposer and coupled between the first bond wire and second bond wire in series with the surface mount component.

23 . The semiconductor device of claim 20 , further including a substrate, wherein the semiconductor die is disposed on the substrate.

24 . The semiconductor device of claim 23 , further including:

a first bond wire coupled between the interposer and the semiconductor die; and

a second bond wire coupled between the interposer and the substrate, wherein the surface mount component is coupled between the first bond wire and second bond wire.

25 . The semiconductor device of claim 24 , further including a transmission line formed over the interposer and coupled between the first bond wire and second bond wire in series with the surface mount component.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (043712/0944) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0921 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043712/0944 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2017
From: PAPILLON, JEAN-MARC
To: SEMTECH CORPORATION
Reel/Frame 042986/0818 →