Storage device, information processing system, method of activating storage device and program
A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.
1. A storage device, comprising:
a first memory that stores data including activation data necessary to activate a host device, an access position of the data being managed based on an address;
a second memory; and
processing circuitry configured to:
perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device;
acquire address information including the address and a data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device;
at activation of the storage device, read data including at least the activation data from the first memory based on the address information and store the data in the second memory;
in response to a read request issued from the host device, transmit the data stored in the second memory to the host device;
store the address information in the second memory; and
store the address information, stored in the second memory, at a specific address of the first memory at a predetermined timing, wherein
the predetermined timing is a timing at which a writing request is issued from the host device or at which a predetermined amount of the address information is stored in the second memory.
2. The storage device according to claim 1 , wherein a read speed of the data of the second memory is faster than a read speed of the data of the first memory.
3. The storage device according to claim 1 , wherein the address information includes sets of a logical address of a read start position of the data and a data amount of the data to be read from the logical address which are arranged in order of read requests from the host device.
4. The storage device according to claim 3 , wherein the data amount of the data to be read from the logical address of the read start position of the data is stored as a number of unit amounts of data writing operation.
5. The storage device according to claim 3 , wherein the address information includes sets of a management unit address, in which the logical address of the read start position of the data is delimited to a size of a management unit of the first memory in the processing circuitry, and a management unit data amount, in which a data amount of the data to be read from the management unit address is delimited in a unit of the size, which are arranged in order of the read requests from the host device.
6. The storage device according to claim 5 , wherein when read requests for data are made continuously or redundantly from the management unit address, the management unit data amount to be described as the address information is increased to collectively describe the management unit addresses.
7. The storage device according to claim 6 , wherein the management unit addresses to be collected is limited to a predetermined number.
8. The storage device according to claim 1 , wherein the processing circuitry is further configured to access a specific address of the first memory at the activation of the storage device and to acquire the address information.
9. The storage device according to claim 1 , wherein the first memory is provided in a non-volatile memory and the second memory is provided in a volatile memory.
10. An information processing system comprising:
the host device configured to perform an activation operation by using activation data, and
the storage device according to claim 1 .
11. An activation method of a storage device including a first memory which stores therein data including activation data necessary to activate a host device, an access position of the data being managed based on an address, a second memory, and a processing circuitry configured to perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device, the activation method comprising:
acquiring address information including the address and a data amount of the data in the first memory, for which a read request is previously issued from the host device;
at activation of the storage device, reading data including at least the activation data from the first memory based on the address information and storing the data in the second memory;
in response to a read request issued from the host device, transmitting the data stored in the second memory to the host device;
storing the address information in the second memory; and
storing the address information, stored in the second memory, at a specific address of the first memory at a predetermined timing, wherein
the predetermined timing is a timing at which a writing request is issued from the host device or at which a predetermined amount of the address information is stored in the second memory.
12. A non-transitory computer-readable recording medium having a program stored therein, the program being executed by a computer including a first memory which stores therein activation data necessary to activate a host device, an access position of the data being managed based on an address, a second memory, and processing circuitry configured to perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device, when the program is executed by the computer, the program causes the processing circuitry to:
acquire address information including the address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device;
at activation of the computer, read data including at least the activation data from the first memory based on the address information and store the data in the second memory;
in response to a read request issued from the host device, transmit the data stored in the second memory to the host device;
store the address information in the second memory; and
store the address information, stored in the second memory, at a specific address of the first memory at a predetermined timing, wherein
the predetermined timing is a timing at which a writing request is issued from the host device or at which a predetermined amount of the address information is stored in the second memory.