Cascode semiconductor device structure and method therefor

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises a first doped region having a first conductivity type adjacent the second major surface;

a heterostructure adjacent the first major surface, wherein the heterostructure comprises:

a channel layer comprising a group III-V material; and

a barrier layer disposed over the channel layer and comprising a group III-V material;

a first electrode disposed proximate to a first portion of the channel layer;

a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;

a control electrode disposed between the first electrode and the second electrode;

a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the first electrode;

a second trench electrode extending through the heterostructure and the semiconductor substrate at least to the first doped region, wherein the second trench electrode electrically connects the control electrode to a third electrode disposed adjacent to the second major surface, and wherein the control electrode is electrically coupled to the third electrode through the semiconductor substrate; and

a rectifier device comprising a second doped region of a second conductivity type opposite to the first conductivity type disposed adjoining the first trench electrode in the semiconductor substrate, wherein:

the rectifier device is electrically coupled to the first trench electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;

the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and

the semiconductor device is configured as a two terminal device.

2. The semiconductor device of claim 1 , wherein:

the semiconductor device comprises a group III-V transistor structure;

the first electrode comprises a source electrode;

the second electrode comprises a drain electrode; and

the first electrode overlaps the first trench electrode.

3. The semiconductor device of claim 2 , wherein the first trench electrode is inset from at least one side surface of the first electrode.

4. The semiconductor device claim 1 , wherein the second doped region and the second electrode overlap.

5. The semiconductor device of claim 1 further comprising a third doped region of the first conductivity type disposed between the semiconductor substrate and the heterostructure.

6. A semiconductor device comprising:

a semiconductor substrate having a first major surface and an opposing second major surface;

a heterostructure adjacent the first major surface, the heterostructure comprising:

a group III-V channel layer; and

a group III-V barrier layer over the group III-V channel layer;

a first electrode disposed proximate to a first portion of the group III-V channel layer;

a second electrode disposed proximate to a second portion of the group III-V channel layer and spaced apart from the first electrode;

a third electrode disposed on the second major surface of the semiconductor substrate;

a control electrode disposed between the first electrode and the second electrode;

a fourth electrode electrically coupled to the first electrode and the semiconductor substrate; and

a rectifier device disposed in the semiconductor substrate and electrically coupled to the fourth electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;

the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and

the control electrode is electrically connected to the third electrode through the semiconductor substrate to provide the semiconductor device as a two terminal device.

7. The semiconductor device of claim 6 , wherein the rectifier device comprises a first doped region having a first conductivity type and adjoining a lower surface of the fourth electrode, and wherein the semiconductor substrate comprises:

a semiconductor region adjacent the first doped region and comprising a second conductivity type opposite to the first conductivity type; and

a second doped region having the second conductivity type and adjoining the second major surface, wherein the second doped region has a higher dopant concentration than the semiconductor region.

8. The semiconductor device of claim 7 , wherein the fourth electrode comprises a first trench electrode extending through the heterostructure, and wherein the control electrode is electrically coupled to the second doped region with a second trench electrode extending through the heterostructure into the semiconductor substrate.

9. The semiconductor device of claim 8 further comprising a third doped region of the second conductivity type disposed adjoining an interface between the heterostructure and the semiconductor substrate.

10. The semiconductor device of claim 8 , wherein the heterostructure is devoid of a channel region proximate to the second trench electrode, and wherein the second trench electrode comprises a trench and a conductive electrode.

11. The semiconductor device of claim 10 , wherein the second trench electrode further comprises a dielectric material between sidewalls of the trench and the conductive electrode.

12. The semiconductor device of claim 6 , wherein:

the rectifier device comprises a Schottky rectifier; and

the third electrode and the second major surface of the semiconductor substrate are configured as a Schottky contact.