Device and method for on-chip mechanical stress sensing

1. An integrated circuit (IC) chip comprising:

a substrate comprising a piezoelectric material having: a first resistivity coefficient for a first direction longitudinal to a crystal axis; and a second resistivity coefficient for a second direction transverse to the crystal axis, the first and second resistivity coefficients having opposite signs; and

a stress sensing element formed in the substrate and configured to conduct current, the stress sensing element comprising: a first resistor aligned to conduct the current primarily in the first direction and a second resistor coupled in series with the first resistor and aligned to conduct the current primarily in the second direction;

a ratio between a resistance of the second resistor and a resistance of the first resistor being proportional to a value α, the value α being equal to a ratio between the first resistivity coefficient and the second resistivity coefficient.

2. The IC chip of claim 1 , wherein a change in the current is proportional to a stress component of a stress applied to the IC chip, the stress component being transverse to the crystal axis.

3. The IC chip of claim 1 , wherein the stress sensing element is a first stress sensing element, the current is a first current, and the IC chip further comprises a second stress sensing element formed in the substrate and configured to conduct a second current, the second stress sensing element comprising: a third resistor aligned to conduct the second current primarily in the first direction; and a fourth resistor coupled in series with the third resistor and aligned to conduct the second current primarily in the second direction; a ratio between a resistance of the third resistor and a resistance of the fourth resistor being proportional to the value α.

4. The IC chip of claim 3 , wherein a change in the second current is proportional to a stress component of the stress applied to the IC chip, the stress component being longitudinal to the crystal axis.

5. The IC chip of claim 4 , wherein the IC further comprises a frequency compensation circuit having inputs coupled to respective outputs from the first stress sensing element and the second stress sensing element.

6. The IC chip of claim 5 , wherein the IC further comprises an oscillator having inputs coupled to frequency adjustment outputs from the compensation circuit.

7. The IC chip of claim 3 , wherein the crystal axis is a first crystal axis, and the IC chip further comprises a third stress sensing element formed in the substrate, the third stress sensing element comprising:

a fifth resistor adapted to be coupled between a first current source and a voltage rail, the fifth resistor aligned to conduct current primarily in a third direction longitudinal to a second crystal axis different from the first crystal axis;

a sixth resistor adapted to be coupled between a second current source and the voltage rail, the sixth resistor aligned to conduct current primarily in a fourth direction transverse to the second crystal axis, a current from the first current source being proportional to a current from the second current source; and

a difference circuit having: a first input adapted to be coupled to a first voltage node between the fifth resistor and the first current source; a second input adapted to be coupled to a second voltage node between the sixth resistor and the second current source; and an output coupled to a third voltage node; the difference circuit configured to make a voltage at the third voltage node proportional to a difference between respective voltages at the first voltage node and the second voltage node.

8. An integrated circuit (IC) chip comprising:

a substrate comprising a piezoelectric material having a first resistivity coefficient for a first direction longitudinal to a crystal axis and a second resistivity coefficient for a second direction transverse to the crystal axis, the first and second resistivity coefficients having opposite signs; and

a stress sensing element formed in the substrate, the stress sensing element comprising

a first resistor adapted to be coupled between a first current source and a voltage rail, the first resistor aligned to conduct current primarily in the first direction;

a first voltage point between the first resistor and the first current source;

a second resistor adapted to be coupled between a second current source and the voltage rail, the second resistor aligned to conduct current primarily in the second direction, a ratio between a current from the first current source and a current from the second current source being proportional to a value α, the value α being equal to a ratio between the second resistivity coefficient and the first resistivity coefficient;

a second voltage point between the second resistor and the second current source; and

a combining circuit configured to add a first voltage at the first voltage point and a second voltage at the second voltage point, and to generate a third voltage responsive to the adding, the third voltage being proportional to a component of stress for the second direction.

9. The IC chip of claim 8 , wherein the stress sensing element is a first stress sensing element, the combining circuit is a first combining circuit, and the IC chip further comprises a second stress sensing element formed in the substrate, the second stress sensing element comprising;

a third resistor adapted to be coupled between a third current source and the voltage rail, the third resistor aligned to conduct current primarily in the first direction;

a fourth voltage point between the third resistor and the third current source;

a fourth resistor adapted to be coupled between a fourth current source and the voltage rail, the fourth resistor aligned to conduct current primarily in the second direction, a ratio between a current from the third current source and a current from the fourth current source being proportional to the value α;

a fifth voltage point between the fourth resistor and the fourth current source; and

a second combining circuit configured to add a fourth voltage at the fourth voltage point and a fifth voltage at the fifth voltage point, and to generate a sixth voltage responsive to the adding, the sixth voltage being proportional to a component of stress for the first direction.

10. The IC chip of claim 9 , wherein the IC further comprises a frequency compensation circuit having inputs coupled to respective outputs from the first stress sensing element and the second stress sensing element.

11. The IC chip of claim 10 , wherein the IC further comprises an oscillator having inputs coupled to frequency adjustment outputs from the compensation circuit.

12. The IC chip of claim 11 , wherein the crystal axis is a first crystal axis, and the IC chip further comprises a third stress sensing element formed in the substrate, the third stress sensing element comprising:

a fifth resistor adapted to be coupled between a fifth current source and the voltage rail, the fifth resistor aligned to conduct current primarily in a third direction longitudinal to a second crystal axis different from the first crystal axis;

a sixth resistor adapted to be coupled between a sixth current source and the voltage rail, the sixth resistor aligned to conduct current primarily in a fourth direction transverse to the second crystal axis, a current from the fifth current source being proportional to a current from the sixth current source; and

a difference circuit having: a first input adapted to be coupled to a first voltage node between the fifth resistor and the fifth current source; a second input adapted to be coupled to a second voltage node between the sixth resistor and the sixth current source; and an output coupled to a third voltage node; the difference circuit configured to make a voltage at the third voltage node proportional to a difference between respective voltages at the first voltage node and the second voltage node.

13. An integrated circuit (IC) chip comprising:

a substrate comprising a piezoelectric material having a first resistivity coefficient for a first direction longitudinal to a crystal axis and a second resistivity coefficient for a second direction transverse to the crystal axis, the first and second resistivity coefficients having opposite signs; and

a stress sensing element formed in the substrate, the stress sensing element comprising:

a first resistor adapted to be coupled between a first current source and a voltage rail, the first resistor aligned to conduct current primarily in the first direction;

a second resistor adapted to be coupled between a second current source and the voltage rail, the second resistor aligned to conduct current primarily in a third direction orthogonal to both the first and second directions, a current from the first current source being proportional to a current from the second current source; and

a difference circuit having: a first input adapted to be coupled to a first voltage node between the first resistor and the first current source; a second input adapted to be coupled to a second voltage node between the second resistor and the second current source; and an output coupled to a third voltage node; the difference circuit configured to make a voltage at the third voltage node proportional to a difference between respective voltages at the first voltage node and the second voltage node.

14. The IC chip of claim 13 wherein the stress sensing element is a first stress sensing element, the difference circuit is a first difference circuit, and the IC chip further comprises a second stress sensing element formed in the substrate, the second stress sensing element comprising:

a third resistor adapted to be coupled between a third current source and the voltage rail, the third resistor aligned to conduct current primarily in the second direction;

a fourth resistor adapted to be coupled between a fourth current source and the voltage rail, the fourth resistor aligned to conduct current primarily in the third direction, a current from the third current source being proportional to a current from the fourth current source; and

a second difference circuit having: a first input adapted to be coupled to a fourth voltage node between the third resistor and the third current source; a second input adapted to be coupled to a fifth voltage node between the fourth resistor and the fourth current source; and an output coupled to a sixth voltage node; the second difference circuit configured to make a voltage at the sixth voltage node proportional to a difference between respective voltages at the fourth voltage node and the fifth voltage node.

15. The IC chip of claim 14 , further comprising a frequency compensation circuit having inputs coupled to respective outputs from the first stress sensing element and the second stress sensing element.

16. The IC chip of claim 15 , wherein the IC further comprises an oscillator having inputs coupled to frequency adjustment outputs from the compensation circuit.

17. The IC chip of claim 14 , wherein the crystal axis is a first crystal axis, and the IC chip further comprises a third stress sensing element formed in the substrate, the third stress sensing element comprising:

a fifth resistor adapted to be coupled between a fifth current source and the voltage rail, the fifth resistor aligned to conduct current primarily in a fourth direction longitudinal to a second crystal axis different from the first crystal axis;

a sixth resistor adapted to be coupled between a sixth current source and the voltage rail, the sixth resistor aligned to conduct current primarily in a fifth direction transverse to the second crystal axis, a current from the fifth current source being proportional to a current from the sixth current source; and

a third difference circuit having: a first input adapted to be coupled to a seventh voltage node between the fifth resistor and the fifth current source; a second input adapted to be coupled to an eighth voltage node between the sixth resistor and the sixth current source; and an output coupled to a ninth voltage node; the third difference circuit configured to make a voltage at the ninth voltage node proportional to a difference between respective voltages at the seventh voltage node and the eighth voltage node.