VARIABLE CACHING STRUCTURE FOR MANAGING PHYSICAL STORAGE
A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.
1 . A method for caching storage management to support guest instruction to native instruction conversion, the method comprising:
accessing a set of guest instructions from guest code;
translating the set of guest instructions into a set of native instructions;
storing the set of native instructions in a native instruction cache;
storing mappings between an identifier based a guest address for the set of guest instructions and an identifier based on a native address for the set of native instructions, the mappings being stored in a conversion look aside buffer; and
storing the set of native instructions in a hierarchical cache where the set of native instructions are removed from the hierarchical cache based on a least recently used replacement scheme.
2 . The method of claim 1 , wherein the hierarchical cache is implemented as a physical stack with blocks of native instructions added having variable sizes.
3 . The method of claim 1 , further comprising:
indexing conversion look aside buffer a portion of the guest address to identify a location in the hierarchical cache with the set of native instructions.
4 . The method of claim 1 , wherein each mapping in the conversion look aside buffer includes a translated block range.
5 . The method of claim 1 , wherein each mapping in the conversion look aside buffer includes management bits to track frequency of hits.
6 . The method of claim 1 wherein each mapping in the conversion look aside buffer includes dynamic branch bias bits to track branch prediction accuracy for branch instructions in the set of native instructions.
7 . The method of claim 1 , wherein the guest address is sub-divided into tags and the conversion look aside buffer is structured as a multi-way tag array.
8 . A device to convert guest instructions to native instructions, the device implementing a method for caching storage management to support guest instruction to native instruction conversion, the device comprising:
fetching logic to access a set of guest instructions from guest code;
conversion logic to translate the set of guest instructions into a set of native instructions, to store the set of native instructions in a native instruction cache, and to store mappings between an identifier based a guest address for the set of guest instructions and an identifier based on a native address for the set of native instructions, the mappings being stored in a conversion look aside buffer;
the conversion look aside buffer to store the mappings; and
a hierarchical cache to store the set of native instructions where the set of native instructions are removed from the hierarchical cache based on a least recently used replacement scheme.
9 . The device of claim 8 , wherein the hierarchical cache is implemented as a physical stack with blocks of native instructions added having variable sizes.
10 . The device of claim 8 , wherein the conversion look aside buffer is indexed using a portion of the guest address to identify a location in the hierarchical cache with the set of native instructions.
11 . The device of claim 8 , wherein each mapping in the conversion look aside buffer includes a translated block range.
12 . The device of claim 8 , wherein each mapping in the conversion look aside buffer includes management bits to track frequency of hits.
13 . The device of claim 8 wherein each mapping in the conversion look aside buffer includes dynamic branch bias bits to track branch prediction accuracy for branch instructions in the set of native instructions.
14 . The device of claim 8 , wherein the guest address is sub-divided into tags and the conversion look aside buffer is structured as a multi-way tag array.
15 . A system including supporting guest instruction to native instruction conversion, the system including caching storage management to support the guest instruction to native instruction conversion, the system comprising:
a processor to execute native instructions;
a pipeline coupled to the processor to implement the guest instruction to native instruction conversion, the pipeline to access a set of guest instructions from guest code, to translate the set of guest instructions into a set of native instructions, to store the set of native instructions in a native instruction cache, and to store mappings between an identifier based a guest address for the set of guest instructions and an identifier based on a native address for the set of native instructions, the mappings being stored in a conversion look aside buffer, the conversion look aside buffer to store the mappings; and
a hierarchical cache to store the set of native instructions where the set of native instructions are removed from the hierarchical cache based on a least recently used replacement scheme.
16 . The system of claim 15 , wherein the hierarchical cache is implemented as a physical stack with blocks of native instructions added having variable sizes.
17 . The system of claim 15 , wherein the conversion look aside buffer is indexed using a portion of the guest address to identify a location in the hierarchical cache with the set of native instructions.
18 . The system of claim 15 , wherein each mapping in the conversion look aside buffer includes a translated block range.
19 . The system of claim 15 , wherein each mapping in the conversion look aside buffer includes management bits to track frequency of hits.
20 . The system of claim 15 , wherein each mapping in the conversion look aside buffer includes dynamic branch bias bits to track branch prediction accuracy for branch instructions in the set of native instructions.