Memory device

1. A memory device comprising:

a plurality of first interconnects provided along a first direction, respectively;

a plurality of second interconnects provided along a second direction different from the first direction, respectively;

a plurality of third interconnects provided along a third direction different from the first and second directions, respectively;

a plurality of memory cells including variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects and coupled with the mutually different second interconnects; and

a plurality of selectors which couple the third interconnects with the first interconnects,

wherein one of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects,

a plurality of gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween, and

wherein in each of the selectors, gates provided on the side surfaces of the semiconductor layer are coupled with each other in common along a second direction, and

the gates are separated between the selectors.

2. The device according to claim 1 , wherein a size of the gate along the first direction is smaller than ½ of a size of the second interconnect along the first direction.

3. The device according to claim 2 , wherein a size of the gate along the first direction is smaller than a minimum processing dimension in a photolithography technology.

4. The device according to claim 1 , wherein the second interconnects alternately belong to the same interconnect group, and

the same voltage is applied to two or more of the second interconnects belonging to the same interconnect group in an operation.

5. The device according to claim 1 , wherein each of the second interconnects belongs to one of two or more interconnect groups, and

the same voltage is applied to one or more of the second interconnects belonging to the same one of the interconnect groups in an operation,

wherein a controller writes data in the memory cells of one of the interconnect groups, and then repeats the writing data to different one of the interconnect groups.

6. The device according to claim 5 , wherein the controller repeats the writing data of the interconnect groups to different one of the first interconnects.

7. The device according to claim 1 , wherein each of the second interconnects belongs to one of two or more interconnect groups, and

the same voltage is applied to one or more of the second interconnects belonging to the same interconnect group in an operation,

wherein a controller writes data in the memory cells of one of the interconnect groups, and then repeats the writing data to different one of the first interconnects.

8. The device according to claim 7 , wherein the controller repeats the writing data of the first interconnects to the different one of the interconnect groups.

9. The device according to claim 1 , wherein the gates formed on two side surfaces of the same semiconductor layer are paired together, and a selection voltage is applied to only one of the paired gates for the same first interconnect during data writing.

10. The device according to claim 1 , wherein the gates formed on two side surfaces of the same semiconductor layer are paired together, and a selection voltage is applied to only one of the paired gates for the same first interconnect during data erasing and reading.