Differential level shift circuit
View Patent ↗In a general aspect, a circuit can include a comparison stage including a plurality of transistors and a current mirror stage including a current mirror. The comparison stage can be configured to produce a cancelling signal before a main signal is produced by the current mirror stage.
1. A circuit, comprising:
a comparison stage including a first transistor of a first conductivity type and a second transistor of the first conductivity type,
the first transistor of the first conductivity type being coupled to a reset input and a set output,
the second transistor of the first conductivity type being coupled to the reset input, the second transistor of the first conductivity type having a gate coupled to a gate of the first transistor of the first conductivity type at the reset input, the first transistor of the first conductivity type having a size larger than a size of the second transistor of the first conductivity type; and
a current mirror stage coupled to the comparison stage and including a first transistor of a second conductivity type in a current mirror configuration with a second transistor of the second conductivity type, the second transistor of the second conductivity type having a drain coupled to a drain of the first transistor of the first conductivity type at a set output.
2. The circuit of claim 1 , wherein the comparison stage is configured to provide a cancelling signal before a main signal is produced by the current mirror stage.
3. The circuit of claim 1 , wherein the first conductivity type is a P-type conductivity, the second conductivity type is a N-type conductivity.
4. The circuit of claim 1 , wherein the set output is a low value when a set input into the comparison stage is at the low value.
5. The circuit of claim 4 , wherein the set output is the low value in response to the set input being at the low value while the reset input is at a value higher than the low value.
6. The circuit of claim 1 , wherein the set output changes to a low value in response to a set input applied to the comparison stage changing to the low value and the reset input changing to a value higher than the low value.
7. The circuit of claim 1 , wherein the circuit is configured to output a comparison of a cancelling signal produced by the comparison stage and a main signal produced by the current mirror stage.
8. A circuit, comprising:
a comparison stage including a first transistor, a second transistor, and a third transistor, the first transistor in the comparison stage having a gate coupled to a gate of the third transistor in the comparison stage at a reset input, the second transistor in the comparison stage having a gate coupled to a set input; and
a current mirror stage including;
a first transistor of a second conductivity type in a first current mirror on a first side of the circuit, and
a second transistor of the second conductivity type included in a second current mirror on a second side of the circuit,
the first transistor in the first current mirror having a source coupled to a source of the second transistor of the second current mirror,
the first transistor in the comparison stage being on the first side of the circuit and being coupled to the first current mirror at a set output, the third transistor in the comparison stage being coupled to the second current mirror, the second transistor of the first conductivity type being on the second side of the circuit and being coupled to second current mirror at a reset output,
the circuit producing a comparison of a cancelling signal produced by the comparison stage and a main signal produced by the current mirror stage as an output,
the comparison stage and the current mirror stage being configured such that the set output has a high value when the set input and the reset input are both the high value.
9. The circuit of claim 8 , wherein the comparison stage further includes:
a fourth transistor in the second side of the circuit and coupled to the reset output.
10. The circuit of claim 8 , wherein the circuit is included in a gate driver controlling a half bridge stage.
11. The circuit of claim 8 , wherein the third transistor included in the comparison stage is larger than the first transistor included in the comparison stage.
12. The circuit of claim 8 , wherein the cancelling signal has a larger magnitude than a magnitude of the main signal so that the cancelling signal cancels out the main signal when the set input and the reset input applied to the comparison stage are the same.
13. The circuit of claim 8 , wherein a comparison of the cancelling signal and the main signal is provided without a glitch handling circuit.
14. A circuit, comprising:
a comparison stage including a plurality of transistors, the plurality of transistors including:
a first transistor of a first conductivity type on a first side of the circuit configured to produce a cancelling signal at a set output at a drain of the first transistor of the first conductivity type in response to a reset input signal received at a reset input at a gate of the transistor of the first conductivity type and at a gate of a second transistor of the first conductivity type,
the first transistor of the first conductivity type being larger than the second transistor of the first conductivity type,
a third transistor of the first conductivity type and a fourth transistor of the first conductivity type each having a gate coupled to a set input on a second side of the circuit; and
a current mirror stage including a first transistor of a second conductivity type included in a current mirror configuration with a second transistor of the second conductivity type on the first side of the circuit, the first transistor of the second conductivity type having a drain coupled to the set output at the drain of the first transistor of the first conductivity type,
the comparison stage configured to produce the cancelling signal before a main signal is produced by the current mirror stage at the set output,
the comparison stage and the current mirror stage being configured such that the set output has a high value when the set input and the reset input are both the high value.
15. The circuit of claim 14 , wherein the first transistor of the first conductivity type is configured to change to at least a partially on-state when producing the cancelling signal at the set output in response to the reset input signal, and
the cancelling signal is produced before the second transistor of the second conductivity type in the current mirror stage is turned to an on-state.
16. The circuit of claim 14 , wherein the first transistor of the first conductivity type is configured to change to at least a partially on-state when producing the cancelling signal at the set output in response to the reset input signal, and
the cancelling signal prevents the main signal from being produced at the set output.
17. The circuit of claim 14 , wherein the cancelling signal has a larger magnitude than a magnitude of the main signal so that the cancelling signal cancels out the main signal when the set input and the reset input applied to the comparison stage are the same.
18. The circuit of claim 14 , wherein the first conductivity type is opposite the second conductivity type.
19. The circuit of claim 14 , wherein a comparison of the cancelling signal and the main signal is provided as the set output without a glitch handling circuit.
20. The circuit of claim 14 , wherein the circuit is included in a gate driver controlling a half bridge stage.