Context-based protection system

1. A system comprising:

a first central processing unit (CPU) configurable to operate in a plurality of protection contexts; and

at least one peripheral module, the peripheral module inaccessible by the first CPU when the first CPU is configured in a first protection context of the plurality of protection contexts and accessible by the first CPU when the first CPU is configured in a second protection context of the plurality of protection contexts,

wherein access to the peripheral module by the first CPU is controlled by a peripheral protection unit disposed within a master/slave interface of a peripheral bus architecture coupled to the at least one peripheral module,

wherein a configuration of the at least one peripheral module is the same when the at least one peripheral module is inaccessible and accessible by the first CPU.

2. The system of claim 1 , further comprising a CPU subsystem the CPU subsystem comprising:

the first CPU;

at least one memory protection unit; and

at least one shared memory protection unit.

3. The system of claim 2 , wherein the at least memory protection unit differentiates between user and privileged accesses from a single bus mater.

4. The system of claim 2 , wherein the at least one shared memory protection unit differentiates between the first and second protection contexts of the plurality of protection contexts and differentiates between secure and non-secure accesses of the first CPU.

5. The system of claim 1 , further comprising a peripheral subsystem comprising:

the at least one peripheral module;

wherein the at least one peripheral protection unit differentiates between:

the first and second protection contexts of the plurality of protection contexts,

secure and non-secure accesses, and

user mode accesses from privileged mode accesses.

6. The system of claim 1 , wherein access to the peripheral module is controlled by values of vector pairs, the first vector of the vector pair for controlling read access to the peripheral module and the second vector of the vector pair for controlling write access to the first vector of the vector pair.

7. The system of claim 1 , wherein the first CPU operation in the second protection context from the first protection context is enabled by an interrupt handler associated with the second protection context.

8. The system of claim 1 , wherein the peripheral module is a memory.

9. The system of claim 1 , further comprising a second CPU configurable to operate in at least one of the plurality of protection contexts.

10. A bus infrastructure comprising a plurality of protection structures, the plurality of protection structures comprising:

a memory protection unit (MPU) assigned to a single bus master, the MPU to differentiate user and privileged accesses from the bus master;

a shared memory protection unit (SMPU) assigned to a plurality of bus masters, the SMPU to differentiate between different protection contexts and to differentiate between secure and non-secure access to a memory; and

a peripheral protection unit (PPU) assigned with a peripheral group, the PPU to differentiate secure and non-secure accesses to the peripheral group, the peripheral protection unit disposed within a master/slave interface of a peripheral bus architecture coupled to the at least one peripheral module,

wherein at least one peripheral of a peripheral group has a configuration that permits secure and non-secure accesses.

11. The bus infrastructure of claim 10 , wherein the PPU differentiates between secure and non-secure accesses to the peripheral group by acknowledging a user mode and a privileged mode, wherein access permitted in a user mode is different than access permitted in a privileged mode.

12. The bus infrastructure of claim 10 , wherein each of the plurality of protection structures are defined by:

an address region; and

access control attributes, wherein the access control attributes specify access control to memory location.

13. The bus infrastructure of claim 10 , wherein the PPU comprises a plurality of protection regions, including at least one of:

all peripherals in the peripheral group; and

a subset of peripherals of the peripheral group, including individual interprocessor communication (IPC) structures, DMA controller channel structures, SMPU protection-required structures, or PPU protection region structures.

14. The bus infrastructure of claim 10 , wherein the bus master is a central processing unit (CPU) operating in a first protection context and a second protection context.

15. The bus infrastructure of claim 14 , wherein the bus master accesses the peripheral group when the CPU operates in the first protection context and is be prohibited from accessing the peripheral group when the CPU operates in the second protection context.

16. The bus infrastructure of claim 10 , wherein access to the peripheral group is controlled by values of vector pairs of the PPU, the first vector of the vector pair for controlling read access to the peripheral group and the second vector of the vector pair for controlling write access to the first vector of the vector pair.

17. A method for controlling access to peripheral modules, the method comprising:

comparing a first protection context of a plurality of protection contexts of a central processing unit (CPU) to an allowed protection context of a first peripheral module;

permitting access to the first peripheral module by the CPU if the first protection context of the CPU matches the allowed protection context of the first peripheral module, access permitted by a first peripheral protection unit disposed within a first master/slave interface of a peripheral bus architecture coupled to the first peripheral module;

altering the protection context of the CPU from the first protection context to a second protection context;

prohibiting access by the first peripheral protection unit to the first peripheral module by the CPU if the second protection context does not match the allowed protection context of the first peripheral module, wherein the first peripheral module has a configuration that is accessible or inaccessible by the CPU; and

permitting access to a second peripheral module by the CPU if the second protection context of the CPU matches the allowed protection context of the second peripheral module, wherein the first protection context is different from the second protection context, access permitted by a second peripheral protection unit disposed within a second master/slave interface of the peripheral bus architecture coupled to the first peripheral module.

18. The method for context-based protection of peripheral modules of claim 17 , wherein access to the peripheral modules is defined by a vector pair for each peripheral module, and wherein the vector pair comprises a first vector of the vector pair for controlling read access to the peripheral module and a second vector of the vector pair for controlling write access to the first vector of the vector pair.