Low-complexity LDPC encoder

1. A computer-implemented method of encoding an information vector, the computer-implemented method comprising:

receiving, by a computer system, the information vector to be encoded into a low-density parity-check (LDPC) codeword;

accessing, by the computer system from a computer memory, a parity-check matrix, wherein:

the parity-check matrix, as stored in the computer memory, is optimized to reduce a computational complexity for generating a parity vector by including a first matrix and a second matrix;

the second matrix, as stored in the computer memory, includes a block diagonal matrix; and

the block diagonal matrix, as stored in the computer memory, includes a set of square submatrices located on a

diagonal of the block diagonal matrix;

generating, by the computer system, an intermediate vector based on the information vector and the first matrix;

generating the parity vector based on the intermediate vector and the second matrix;

generating, by the computer system, the LDPC codeword including the information vector and the parity vector; and

storing the LDPC codeword in the computer memory.

2. The computer-implemented method of claim 1 , wherein storing the LDPC codeword comprises writing the LDPC codeword to the computer memory.

3. The computer-implemented method of claim 1 , wherein generating the parity vector comprises:

dividing, by the computer system, the intermediate vector into a set of intermediate sub-vectors, each intermediate sub-vector corresponding to a square submatrix of the set of square submatrices; and

for each intermediate sub-vector of the set of intermediate sub-vectors,

generating, by the computer system, a corresponding parity sub-vector of a set of parity sub-vectors for the parity vector based on the intermediate sub-vector and the corresponding square submatrix.

4. The computer-implemented method of claim 3 , wherein generating the corresponding parity sub-vector of the set of parity sub-vectors based on the intermediate sub-vector and the corresponding square submatrix comprises:

multiplying the intermediate sub-vector and an inverse of a transpose of the corresponding square submatrix.

5. The computer-implemented method of claim 3 , wherein:

each parity sub-vector is generated by a separate operating unit of the computer system; and

the parity sub-vectors are generated in parallel by corresponding operating units of the computer system.

6. The computer-implemented method of claim 3 , wherein:

the information vector includes K bits;

the LDPC codeword includes N bit;

the parity-check matrix includes an (N−K)×N matrix;

the first matrix includes an (N−K)×K matrix; and

the second matrix includes an (N−K)×(N−K) matrix.

7. The computer-implemented method of claim 6 , wherein:

the set of square submatrices includes a plurality of aixai matrixes, wherein i varies between 1 and N−K; and

the set of intermediate sub-vectors includes a plurality of ai-bit sub-vectors.

8. The computer-implemented method of claim 1 , wherein generating the intermediate vector comprises:

multiplying the information vector and a transpose of the first matrix.

9. The computer-implemented method of claim 1 , wherein generating the LDPC codeword comprises:

concatenating the information vector and the parity vector.

10. A system comprising:

one or more memories configured to store a parity-check matrix, wherein:

the parity-check matrix, as stored in the one or more memories, is optimized to reduce a computational complexity for generating a parity vector by including a first matrix and a second matrix;

the second matrix, as stored in the one or more memories, includes a block diagonal matrix; and

the block diagonal matrix, as stored in the one or more memories, includes a set of square submatrices located on a diagonal of the block diagonal matrix; and

a low-density parity-check (LDPC) encoder coupled to the one or more memories, wherein the LDPC encoder is configured to:

receive an information vector to be encoded into an LDPC codeword;

access the parity-check matrix;

generate an intermediate vector based on the information vector and the first matrix;

generate the parity vector based on the intermediate vector and the second matrix;

generate the LDPC codeword including the information vector and the parity vector; and

store the LDPC codeword in the one or more memories.

11. The system of claim 10 , wherein the system further comprises a transmit unit, the transmit unit configured to:

write the LDPC codeword to the one or more memories.

12. The system of claim 10 , wherein generating the parity vector comprises:

dividing the intermediate vector into a set of intermediate sub-vectors, each intermediate sub-vector corresponding to a square submatrix of the set of square submatrices; and

for each intermediate sub-vector of the set of intermediate sub-vectors,

generating a corresponding parity sub-vector of a set of parity sub-vectors for the parity vector based on the intermediate sub-vector and the corresponding square submatrix.

13. The system of claim 12 , wherein:

the LDPC encoder includes a set of operating units;

each operating unit of the set of operating units is configured to generate a corresponding parity sub-vector; and

the set of operating units generates the set of parity sub-vectors in parallel.

14. The system of claim 12 , wherein the LDPC encoder is configured to generate the corresponding parity sub-vector of the set of parity sub-vectors by multiplying the intermediate sub-vector and an inverse of a transpose of the corresponding square submatrix.

15. The system of claim 10 , wherein the LDPC encoder is configured to generate the intermediate vector by multiplying the information vector and a transpose of the first matrix.

16. The system of claim 10 , wherein the LDPC encoder includes a multiplexer, the multiplexer configured to generate the LDPC codeword by concatenating the information vector and the parity vector.

17. A non-transitory computer-readable storage medium storing a plurality of instructions that, upon execution on a system, cause the system to perform operations comprising:

receiving an information vector to be encoded into a low-density parity-check (LDPC) codeword;

accessing a parity-check matrix from the non-transitory computer-readable storage medium of the system, wherein:

the parity-check matrix, as stored in the non-transitory computer-readable storage medium, is optimized to reduce a computational complexity for generating a parity vector by including a first matrix and a second matrix;

the second matrix, as stored in the non-transitory computer-readable storage medium, includes a block diagonal matrix; and

the block diagonal matrix, as stored in the non-transitory computer-readable storage medium, includes a set of square submatrices located on a diagonal of the block diagonal matrix;

generating an intermediate vector based on the information vector and the first matrix;

generating the parity vector based on the intermediate vector and the second matrix;

generating the LDPC codeword including the information vector and the parity vector; and

storing the LDPC codeword in the non-transitory computer-readable storage medium.

18. The non-transitory computer-readable storage medium of claim 17 , wherein storing the LDPC codeword comprises writing the LDPC codeword to the non-transitory computer-readable storage medium.

19. The non-transitory computer-readable storage medium of claim 17 , wherein generating the intermediate vector comprises:

multiplying the information vector and a transpose of the first matrix.

20. The non-transitory computer-readable storage medium of claim 17 , wherein generating the parity vector comprises:

dividing the intermediate vector into a set of intermediate sub-vectors, each intermediate sub-vector corresponding to a square submatrix of the set of square submatrices; and

performing, in parallel and for each intermediate sub-vector of the set of intermediate sub-vectors:

generating a corresponding parity sub-vector of a set of parity sub-vectors for the parity vector by multiplying a respective intermediate sub-vector of the set of intermediate sub-vectors and an inverse of a transpose of a corresponding square submatrix of the set of square submatrices.