Memory system including a plurality of memory devices having different latencies and operation method thereof
A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory devices have different latencies each other, and a controller transceiving a data with the memory devices through the data bus, wherein the controller may transceive a data with the memory devices during a time corresponding to a data burst length for a moment being the each latencies of the memory devices after transmitting same control signals to the memory devices.
1. A memory system, comprising:
a plurality of memory devices sharing a common data bus and a common control bus; and
a controller suitable for:
controlling the memory devices and transceiving data with the memory devices through the common data bus;
setting latencies for the plurality of memory devices using additive latencies, each of the additive latencies corresponding to each of the memory devices; and
transceiving data with the memory devices, respectively, in response to a single control signal, during clock intervals, wherein each of the clock intervals is corresponding to a data burst length based on a corresponding set latency among the set latencies.
2. The memory system of claim 1 ,
wherein the controller further sets the additive latencies to have values increasing by a time interval corresponding to the data burst length.
3. The memory system of claim 2 , wherein the smallest value of the additive latencies is 0.
4. The memory system of claim 3 , wherein the control signal is a write command.
5. The memory system of claim 4 , wherein the controller transmits data corresponding to the write command to each of the memory devices during a clock interval corresponding to the data burst length based on the corresponding latency among the set latencies, in response to the write command.
6. The memory system of claim 5 , each of the latencies further includes a CAS write latency.
7. The memory system of claim 3 , wherein the control signal is a read command.
8. The memory system of claim 7 , wherein the controller receives data corresponding to the read command from each of the memory devices during a clock interval corresponding to the data burst length based on the corresponding latency among the set latencies, in response to the read command.
9. The memory system of claim 8 , wherein each of the latencies further includes a CAS latency.
10. The memory system of claim 3 , wherein the control signal includes chip selection signal, command signal and address signal.
11. A method for operating a memory system including a plurality of memory devices, the method comprising:
transmitting a single write command to the memory devices;
setting latencies for the plurality of memory devices using additive latencies, each of the additive latencies corresponding to each of the memory devices; and
transmitting data corresponding to the write command to each of the memory devices, respectively, in response to the write command, during clock intervals, wherein each of the clock intervals is corresponding to a data burst length based on a corresponding set latency among the set latencies.
12. The method of claim 11 ,
further comprising setting the additive latencies to have values increasing by a time interval corresponding to the data burst length.
13. The method of claim 12 , wherein the smallest value of the additive latencies is 0.
14. The method of claim 13 , each of the latencies further includes and a CAS write latency.
15. The method of claim 13 , wherein the write command includes chip selection signal, command signal and address signal.
16. A method for operating a memory system including a plurality of memory devices, the method comprising:
transmitting a single read command to the memory devices;
setting latencies for the plurality of memory devices using additive latencies, each of the additive latencies corresponding to each of the memory devices; and
receiving data corresponding to the read command from the memory devices, respectively, in response to the read command, during clock intervals, wherein each of the clock intervals is corresponding to a data burst length based on a corresponding set latency among the set latencies.
17. The method of claim 16 ,
further comprising setting the additive latencies to have values increasing by a time interval corresponding to the data burst length.
18. The method of claim 17 , wherein the smallest value of the additive latencies is 0.
19. The method of claim 18 , wherein each of the latencies further includes and a CAS latency.
20. The method of claim 18 , wherein the read command includes chip selection signal, command signal and address signal.