IP Library Granted Patent US 10,128,330
Granted Patent B1
US 10,128,330 · App. 15/655,532 · Granted Nov 13, 2018

Semiconductor device with a buried junction layer having an interspersed pattern of doped and counter-doped materials

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Quick Facts
Patent No.
US 10,128,330
App. No.
15/655,532
Granted
Nov 13, 2018
Kind
B1
Abstract

A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.

Claims (17)

1. A semiconductor device that comprises:

three terminals;

a drift region between two of the terminals, wherein the drift region includes an upper drift layer, a lower drift layer, and

a plurality of buried junction layers between the upper and lower drift layers, with an intermediate drift layer separating each pair of adjacent buried junction layers,

wherein the upper and lower drift layers have a first type of doping,

wherein each buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers, and

wherein the interspersed patterns corresponding to the plurality of buried junction layers are not aligned.

2. The semiconductor device of claim 1 , wherein the interspersed pattern comprises spaced islands of the first material separated by the second material.

3. The semiconductor device of claim 1 , wherein the interspersed pattern comprises spaced lines of the first material separated by the second material.

4. The semiconductor device of claim 3 , wherein at least some of the spaced lines intersect each other.

5. A semiconductor device that comprises:

three terminals;

a drift region between two of the terminals, wherein the drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers,

wherein the upper and lower drift layers have a first type of doping, and

wherein the buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers,

wherein the spacing of interspersions within an active region is constant, and wherein the spacing of interspersions outside the active region is increased relative the spacing of interspersions within the active region.

6. The semiconductor device of claim 5 , wherein the spacing of interspersions outside an active region continually increases as a function of distance from the active region.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2017
From: WALL, RALPH N.; LEE, MENG-CHIA
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043057/0785 →