Electrical connector with improved impedance characteristics
A shroud that forms part of an electrical connector for securing a plurality of circuit wafers within the electrical connector includes a top wall, a bottom wall, and a plurality of vertical members extending between the top and bottom walls that define a plurality of slots for receiving the plurality of circuit wafers. Each vertical member includes a first side that faces a second side of an adjacent vertical member. The first side defines top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a first distance, and first and second recessed surface regions between the top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a second distance that is greater than the first distance. The first and second recessed surface regions are positioned so as to prevent direct contact between the vertical members and one or more high-frequency traces disposed on the plurality of circuit wafers.
1. A shroud that forms part of an electrical connector for securing a plurality of circuit wafers within the electrical connector, the shroud comprising:
a top wall;
a bottom wall;
a plurality of vertical members extending between the top and bottom walls that define a plurality of slots for receiving the plurality of circuit wafers, each vertical member including a first side that faces a second side of an adjacent vertical member;
wherein the first side defines top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a first distance, and first and second recessed surface regions between the top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a second distance that is greater than the first distance, wherein the first and second recessed surface regions are positioned so as to prevent direct contact between the vertical members and one or more high-frequency traces disposed on the plurality of circuit wafers.
2. The shroud according to claim 1 , wherein the top surface region extends from the top wall to a top section of the first recessed surface region and the bottom surface region extends from the bottom wall to a bottom section of the second recessed surface region.
3. The shroud according to claim 1 , wherein the middle surface region is centered between the top wall and the bottom wall.
4. The shroud according to claim 1 , wherein a height of the first and second recessed surface regions are about 5.0 mm.
5. The shroud according to claim 1 , wherein the first distance is about 0.45 mm and the second distance is about 0.60 mm.
6. The shroud according to claim 1 , wherein a surface of the second side is substantially flat.
7. An electrical connector comprising:
a bottom housing;
a plurality of circuit wafers disposed within the bottom housing, each circuit wafer includes one or more high-frequency traces for communicating high-frequency signals; and
a shroud that forms a top of the electrical connector that is configured to engage the bottom housing to secure the plurality of circuit wafers between the bottom housing and the shroud, the shroud comprising:
a top wall;
a bottom wall;
a plurality of vertical members extending between the top and bottom walls that define a plurality of slots for maintaining spacing between the plurality of circuit wafers, each vertical member including a first side that faces a second side of an adjacent vertical member;
wherein the first side defines top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a first distance, and first and second recessed surface regions between the top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a second distance that is greater than the first distance, wherein the first and second recessed surface regions are positioned so as to prevent direct contact between the vertical members and the one or more high-frequency traces disposed on the a plurality of circuit wafers to thereby improve impedance characteristics of the electrical connector.
8. The electrical connector according to claim 7 , wherein the top surface region extends from the top wall to a top section of the first recessed surface region and the bottom surface region extends from the bottom wall to a bottom section of the second recessed surface region.
9. The electrical connector according to claim 7 , wherein the middle surface region is centered between the top wall and the bottom wall.
10. The electrical connector according to claim 7 , wherein a height of the first and second recessed surface regions is about 5.0 mm.
11. The electrical connector according to claim 7 , wherein the first distance is about 0.45 mm and the second distance is about 0.60 mm.
12. The electrical connector according to claim 7 , wherein a surface of the second side is substantially flat.
13. The electrical connector according to claim 7 , wherein the plurality of circuit wafers includes a first group of circuit wafers and a second group of circuit wafers, wherein an arrangement of the one or more high-frequency traces on the first group of circuit wafers is different from an arrangement of the one or more high frequency traces on the second group of circuit wafers; and
wherein the first and second recessed surface regions of the vertical members are arranged in a same relative position for each vertical member and arranged so as to prevent direct contact between the vertical members and the one or more high-frequency traces disposed on both the first and second group of circuit wafers.
14. An electrical product that includes an electrical connector, the electrical connector comprises:
a bottom housing;
a plurality of circuit wafers disposed within the bottom housing, each circuit wafer includes one or more high-frequency traces for communicating high-frequency signals; and
a shroud that forms a top of the electrical connector that is configured to engage the bottom housing to secure the plurality of circuit wafers between the bottom housing and the shroud, the shroud comprising:
a top wall;
a bottom wall;
a plurality of vertical members extending between the top and bottom walls that define a plurality of slots for maintaining spacing between the plurality of circuit wafers, each vertical member including a first side that faces a second side of an adjacent vertical member;
wherein the first side defines top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a first distance, and first and second recessed surface regions between the top, middle, and bottom surface regions that are spaced apart from the second side of the adjacent vertical member by a second distance that is greater than the first distance, wherein the first and second recessed surface regions are positioned so as to prevent direct contact between the vertical members and the one or more high-frequency traces disposed on the a plurality of circuit wafers to thereby improve impedance characteristics of the electrical connector.
15. The electrical product according to claim 14 , wherein the top surface region extends from the top wall to a top section of the first recessed surface region and the bottom surface region extends from the bottom wall to a bottom section of the second recessed surface region.
16. The electrical product according to claim 14 , wherein the middle surface region is centered between the top wall and the bottom wall.
17. The electrical product according to claim 14 , wherein a height of the first and second recessed surface regions is about 5.0 mm.
18. The electrical product according to claim 14 , wherein the first distance is about 0.45 mm and the second distance is about 0.60 mm.
19. The electrical product according to claim 14 , wherein a surface of the second side is substantially flat.
20. The electrical product according to claim 14 , wherein the plurality of circuit wafers includes a first group of circuit wafers and a second group of circuit wafers, wherein an arrangement of the one or more high-frequency traces on the first group of circuit wafers is different from an arrangement of the one or more high frequency traces on the second group of circuit wafers; and
wherein the first and second recessed surface regions of the vertical members are arranged in a same relative position for each vertical member and arranged so as to prevent direct contact between the vertical members and the one or more high-frequency traces disposed on both the first and second group of circuit wafers.