Semiconductor device having self-isolating bulk substrate and method therefor
View Patent ↗A semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Trench isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent trench isolation regions.
1. A method for forming a semiconductor device structure comprising:
providing a self-isolating bulk semiconductor substrate having first and second opposing major surfaces, wherein the self-isolating bulk semiconductor substrate comprises:
a floating buried doped region of a first conductivity type;
a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface, wherein the doped region abuts the floating buried doped region; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
providing a trench isolation region extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein the floating buried doped region abuts the trench isolation region; and
providing a semiconductor device disposed within the doped region.
2. The method of claim 1 , wherein providing the self-isolating bulk substrate comprises providing the doped region and the semiconductor region absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region.
3. The method of claim 2 , wherein providing the self-isolating bulk semiconductor substrate comprises providing the self-isolating bulk substrate absent any laterally extending buried oxides or SOI structures that partially or completely vertically separate the doped region from the semiconductor region.
4. The method of claim 1 , wherein providing the self-isolating bulk substrate comprises providing the floating buried doped region having a varying dopant concentration.
5. The method of claim 4 , wherein providing the floating buried doped region comprises:
providing a first region adjoining the doped region; and
providing a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region.
6. The method of claim 5 , wherein providing the floating buried doped region further comprises providing a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.
7. The method of claim 1 , wherein providing the semiconductor device comprises a forming power MOS device.
8. The method of claim 1 further comprising forming a shielding structure disposed within the doped region laterally and vertically enclosing the semiconductor device.
9. The method of claim 8 , wherein:
forming the shielding structure comprises:
forming a buried layer portion of the first conductivity type disposed between the floating buried doped region and the semiconductor device; and
forming a sinker portion of the first conductivity type laterally disposed between the trench isolation region and the semiconductor device, wherein the sinker portion physically contacts the buried layer portion of the shielding structure; and
providing the semiconductor device comprises forming s a CMOS device.
10. The method of claim 1 , wherein providing the semiconductor device comprises forming at least one second doped region of the first conductivity type extending from the first major surface into the doped region and vertically separated from the floating buried doped region by the doped region.
11. A semiconductor device structure comprising:
a bulk semiconductor substrate having first and second opposing major surfaces, wherein the bulk semiconductor substrate comprises:
a floating buried doped region of a first conductivity type;
a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface, and wherein the doped region abuts the floating buried doped region; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
an isolation trench having a pair of laterally separated isolation trench portions in a cross-sectional view extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, and wherein the floating buried doped region abuts the pair of laterally separated isolation trench portions in the cross-sectional view; and
a semiconductor device disposed within the doped region between the pair of laterally separated isolation trench portions, wherein:
the isolation trench comprises:
a trench;
a dielectric material lining surfaces of the trench; and
a conductive material disposed adjacent the dielectric material, wherein the dielectric material physically separates the conductive material from the bulk semiconductor substrate.
12. The structure of claim 11 , wherein the bulk semiconductor substrate is provided absent any laterally extending buried oxides or SOI structures that partially or completely vertically separate the doped region from the semiconductor region.
13. The structure of claim 11 , wherein the floating buried doped region comprises:
a first region adjoining the doped region;
a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and
a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.
14. The structure of claim 11 further comprising a shielding structure disposed within the doped region laterally and vertically enclosing the semiconductor device, wherein the shielding structure comprises:
a buried layer portion of the first conductivity type disposed between the floating buried doped region and the semiconductor device; and
a sinker portion of the first conductivity type laterally disposed between the pair of laterally separated isolation trench portions in the cross-sectional view and the semiconductor device, wherein the sinker portion physically contacts the buried layer portion of the shielding structure.
15. The structure of claim 11 , wherein the doped region and the semiconductor region are provided absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region.
16. A method for forming a semiconductor device structure, comprising:
providing a self-isolating bulk semiconductor substrate having first and second opposing major surfaces, wherein the self-isolating bulk semiconductor substrate comprises:
a floating buried doped region of a first conductivity type;
a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface, wherein the doped region abuts the floating buried doped region; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
providing an isolation trench having a pair of laterally separated isolation trench portions in a cross-sectional view extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, and wherein the floating buried doped region abuts the pair of laterally separated isolation trench portions in the cross-sectional view; and
providing a semiconductor device disposed within the doped region.
17. The method of claim 16 , wherein providing the isolation trench comprises:
providing a trench;
providing a dielectric material lining surfaces of the trench; and
providing a conductive material disposed adjacent the dielectric material, wherein the dielectric material physically separates the conductive material from the bulk semiconductor substrate.
18. The method of claim 16 , wherein providing the self-isolating bulk semiconductor substrate comprises providing the floating buried doped region comprising:
a first region adjoining the doped region; and
a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region.
19. The method of claim 16 further comprising forming a shielding structure disposed within the doped region laterally and vertically enclosing the semiconductor device.
20. The method of claim 16 , wherein providing the semiconductor device comprises forming at least one second doped region of the first conductivity type extending from the first major surface into the doped region and vertically separated from the floating buried doped region by the doped region.