III-P LIGHT EMITTING DEVICE WITH A SUPERLATTICE
A device includes a semiconductor structure comprising a III-P light emitting layer disposed between an n-type region and a p-type region. The n-type region includes a superlattice. The superlattice includes a plurality of stacked layer pairs, each layer pair including a first layer and a second layer. The first layer has a smaller aluminum composition than the second layer.
1 . A device comprising:
a semiconductor structure comprising a III-P light emitting layer disposed between an n-type region and a p-type region, the n-type region comprising a superlattice; and
an n-contact metal on and in contact with a surface of the superlattice opposite the III-P light emitting layer,
the superlattice comprising a plurality of stacked layer pairs, each layer pair comprising a first layer of Al x Ga 1−x InP where 0<x<1 and a second layer of Al y Ga 1−y InP where 0<y<1, the first layer having a smaller aluminum composition than the second layer.
2 . The device of claim 1 further comprising:
a bottom contact disposed on the p-type region.
3 . The device of claim 1 wherein 0.3≦x≦0.4 and 0.4≦y≦0.5.
4 . The device of claim 1 wherein 0.2≦x≦0.5 and 0.3≦y≦0.65.
5 . The device of claim 1 wherein the first and second layers are doped with an n-type dopant.
6 . The device of claim 1 wherein at least one of the first and second layers is strained relative to a growth substrate on which the semiconductor structure is grown.
7 . The device of claim 1 wherein the superlattice is lattice matched to a growth substrate on which the semiconductor structure is grown.
8 . A method comprising:
growing an n-type superlattice on a growth substrate, the superlattice comprising a plurality of stacked layer pairs, each layer pair comprising a first layer of AlGaInP and a second layer of AlGaInP, the first layer having a smaller aluminum composition than the second layer;
forming a first metal contact on the p-type region;
growing a light emitting region directly on the n-type superlattice;
growing a p-type region on the light emitting region;
removing the growth substrate to expose a surface of the superlattice; and
forming a second metal contact directly on the exposed surface of the superlattice.
9 . The method of claim 8 wherein 0.2≦x≦0.5 and 0.3≦y≦0.65.
10 . The method of claim 8 further comprising lattice matching the superlattice to the growth substrate.
11 . The method of claim 8 further comprising growing at least one of the first and second layers strained relative to the growth substrate.
12 . The method of claim 8 further comprising roughening or patterning the exposed surface of the superlattice.
13 . The method of claim 8 wherein forming a second metal contact directly on the exposed surface of the superlattice comprises:
forming a metal layer directly on the surface of the superlattice; and
patterning the metal layer to form a shaped second metal contact, the shape having a width no less than 1 micron and no greater 30 microns in a plan view.
14 . The device of claim 1 wherein the superlattice layers are doped with a doping profile changing across the superlattice.
15 . The device of claim 1 wherein the first layers are more highly doped than the second layers.
16 . The device of claim 1 , wherein the second layers are more highly doped than the first layers.
17 . The device of claim 1 , wherein the n-contact layer is patterned to have a shape, the shape having a width no less than 1 micron and no greater 30 microns in a plan view.
18 . The device of claim 17 , wherein the shape has a width no less than 1 micron and no greater than 20 microns.
19 . A device comprising:
a semiconductor structure comprising a III-P light emitting layer disposed between an n-type region and a p-type region, the n-type region comprising a superlattice;
a current spreading layer on and in contact with a surface of the superlattice opposite the III-P light emitting layer; and
an n-contact on and in contact with the current spreading layer,
the superlattice comprising a plurality of stacked layer pairs, each layer pair comprising a first layer of Al x Ga 1−x InP where 0<x<1 and a second layer of Al y Ga 1−y InP where 0<y<1, the first layer having a smaller aluminum composition than the second layer.
20 . The device of claim 19 , wherein the current spreading layer comprises indium tin oxide or zinc oxide.