IMAGING DEVICE, IMAGING MODULE, ELECTRONIC DEVICE, AND IMAGING SYSTEM

1 . An imaging device having a neuron in a neural network, comprising:

a plurality of first pixels;

a first circuit;

a second circuit; and

a third circuit,

wherein each of the plurality of first pixels comprises a photoelectric conversion element,

wherein the photoelectric conversion element is electrically connected to the first circuit,

wherein the first circuit is electrically connected to the second circuit,

wherein the second circuit is electrically connected to the third circuit,

wherein each of the plurality of first pixels generates an input signal of the neuron in the neural network,

wherein the first circuit, the second circuit, and the third circuit serve as the neuron, and

wherein the third circuit comprises an interface connected to the neural network.

2 . The imaging device according to claim 1 ,

wherein each of the plurality of first pixels is configured to convert received light into an analog signal,

wherein the first circuit is configured to amplify the analog signal,

wherein the second circuit is configured to add a plurality of amplified analog signals,

wherein the third circuit is configured to convert added analog signals into feature data by using an activation function, and

wherein the third circuit is configured to determine the feature data.

3 . The imaging device according to claim 1 ,

wherein the first circuit comprises an amplifier circuit, a first memory circuit, and a first adder circuit,

wherein the second circuit comprises a second adder circuit,

wherein the third circuit comprises a first arithmetic circuit and a second memory circuit,

wherein each of the plurality of first pixels is configured to convert light into a first signal to output,

wherein the amplifier circuit is configured to amplify the first signal at an amplification factor held in the first memory circuit,

wherein the first adder circuit is configured to add an offset voltage to the first signal that is amplified,

wherein the first adder circuit is configured to output a second signal that is a result of addition of the offset voltage to the first signal,

wherein the second adder circuit is configured to add a plurality of second signals,

wherein the second adder circuit is configured to output a third signal that is obtained by adding the plurality of second signals and that is an analog signal,

wherein the first arithmetic circuit is configured to determine and binarize the third signal,

wherein the first arithmetic circuit is configured to supply the signal that is binarized to the second memory circuit as a feature data, and

wherein the second memory circuit is configured to output the feature data to the neural network.

4 . The imaging device according to claim 1 ,

wherein each of the plurality of first pixels is configured to convert received light into an analog signal and output the analog signal as a fourth signal,

wherein the first circuit is configured to convert the fourth signal into a digital signal,

wherein the first circuit is configured to generate a fifth signal having a feature by classifying a level of the digital signal using bit shift,

wherein the second circuit is configured to extract and count the feature of the fifth signal,

wherein the third circuit is configured to convert a result of count into a feature data by using an activation function, and

wherein the third circuit is configured to determine the feature data.

5 . The imaging device according to claim 4 ,

wherein the first circuit comprises a first input selection circuit, an analog-to-digital converter circuit, a first determination circuit, and a first memory circuit,

wherein the second circuit comprises a second input selection circuit and a feature extraction circuit,

wherein the third circuit comprises a second determination circuit and a second memory circuit,

wherein the first input selection circuit is configured to select any of a plurality of fourth signals,

wherein the analog-to-digital converter circuit is configured to convert the fourth signal that is selected into the digital signal,

wherein the first determination circuit is configured to amplify the digital signal by a power of two in accordance with an amount of bit shift that is selected,

wherein the first determination circuit is configured to determine a level of the digital signal that is amplified, in accordance with the amount of bit shift,

wherein the first determination circuit is configured to supply a determination result to the first memory circuit as the fifth signal,

wherein the second input selection circuit is configured to sequentially select the fifth signal held in the first memory circuit and output the selected fifth signal to the feature extraction circuit,

wherein the feature extraction circuit is configured to count the fifth signal with the feature,

wherein the second determination circuit compares a count result with a supplied condition,

wherein the second determination circuit is configured to supply a comparison result to the second memory circuit as feature data, and

wherein the second memory circuit is configured to output the feature data to the neural network.

6 . The imaging device according to claim 1 , further comprising:

a signal line; and

a second analog-to-digital converter circuit,

wherein each of the plurality of first pixels is configured to convert received light into an analog signal, and

wherein the analog signal is supplied to the second analog-to-digital converter circuit through the signal line from each of the plurality of first pixels.

7 . The imaging device according to claim 4 ,

wherein the third circuit comprises a selection circuit, and

wherein the feature data is divided into pieces of data each having a selected length and output to the neural network.

8 . The imaging device according to claim 1 ,

wherein each of the plurality of first pixels comprises a first transistor, and

wherein the first transistor comprises a metal oxide in a semiconductor layer.

9 . The imaging device according to claim 8 ,

wherein the first transistor included in each of the plurality of first pixels comprises a metal oxide in the semiconductor layer, and

wherein a second transistor included in a circuit other than the plurality of first pixels comprises single crystal silicon in a semiconductor layer.

10 . The imaging device according to claim 8 ,

wherein the first transistor comprises a back gate.

11 . The imaging device according to claim 8 ,

wherein the first transistor comprises a region overlapping with the photoelectric conversion element.

12 . An imaging module comprising:

the imaging device according to claim 1 ; and

a lens.

13 . An electronic device comprising:

the imaging device according to claim 1 ; and

a display device.