IP Library Granted Patent US 10,243,032
Granted Patent B2
US 10,243,032 · App. 15/661,514 · Granted Mar 26, 2019

Display device

Inventor: Toshihiro Sato (Minato-ku, JP)
Assignee: Japan Display Inc.
H01L27/3274H01L27/15H01L29/06H01L29/786H01L33/06H01L51/502H01L51/5296H05B33/14H01L27/286H01L27/322H01L51/0554
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Quick Facts
Patent No.
US 10,243,032
App. No.
15/661,514
Granted
Mar 26, 2019
Kind
B2
Abstract

A selection transistor and a light-emitting transistor are formed in a pixel. The selection transistor includes a gate electrode connected to a scan line, a first source/drain electrode connected to a signal line, and a second source/drain electrode. The light-emitting transistor includes a gate electrode connected to the second source/drain electrode of the selection transistor, a first electrode connected to a first line, a second electrode connected to a second line, and a channel layer including quantum dots. The light-emitting transistor controls the quantum dots to emit light by a carrier flowing through the channel layer.

Claims (51)

1. A display device comprising:

a plurality of pixels;

a scan line;

a signal line;

a first line;

a second line; and

an insulating layer that includes an opening in each of the plurality of pixels,

wherein at least one pixel among the plurality of pixels includes

a selection transistor that includes a gate electrode connected to the scan line, a first source/drain electrode connected to the signal line, and a second source/drain electrode, and

a light-emitting transistor that includes a gate electrode to which a voltage corresponding to a gradation value of the at least one pixel is applied through the second source/drain electrode of the selection transistor, a first electrode connected to the first line, a second electrode connected to the second line, and a channel layer including quantum dots, and controls the quantum dots to emit light by carriers flowing through the channel layer,

the channel layer of the light-emitting transistor is disposed inside the opening of the insulating layer,

the first electrode and the second electrode of the light-emitting transistor are formed on upper sides of the channel layer and the insulating layer, and

the gate electrode of the light-emitting transistor includes a reflecting surface that reflects light from the quantum dots.

2. The display device according to claim 1 ,

wherein the channel layer of the light-emitting transistor is formed on an upper side of the gate electrode of the light-emitting transistor.

3. The display device according to claim 1 ,

wherein the gate electrode, the first electrode, and the second electrode of the light-emitting transistor are formed on an upper side of the channel layer.

4. The display device according to claim 1 ,

wherein the opening of the insulating layer has an inclined surface on an inner peripheral surface thereof,

the channel layer of the light-emitting transistor and the gate electrode of the light-emitting transistor are formed inside the opening of the insulating layer, and

an outer peripheral portion of the gate electrode of the light-emitting transistor is formed on the inclined surface of the opening of the insulating layer.

5. The display device according to claim 1 ,

wherein the light-emitting transistor includes an auxiliary electrode that is formed on an opposite side to the gate electrode across the channel layer therebetween.

6. The display device according to claim 1 ,

wherein the at least one pixel of the plurality of pixels has a first pixel and a second pixel adjacent to the first pixel, and

a size of the quantum dots of the first pixel and a size of the quantum dots of the second pixel are different from each other.

7. The display device according to claim 1 ,

wherein the plurality of pixels has a first pixel, a second pixel, a third pixel, and a fourth pixel,

the first pixel and the second pixel form a first row,

the third pixel and the fourth pixel form a second row, and

one line of the first line and the second line is located between the first row and the second row, and overlaps with the channel layer of the first pixel, the second pixel, the third pixel, and the fourth pixel in plan view.

8. The display device according to claim 1 ,

wherein the first line and the second line are alternately arranged in plan view.

9. The display device according to claim 1 ,

wherein the channel layer of the light-emitting transistor includes a first region in contact with the first electrode, a second region in contact with the second electrode, and a third region between the first region and the second region, and

impurities are added into at least one region of the first region and the second region.

10. The display device according to claim 1 ,

wherein a concentration of the quantum dots in the channel layer has a gradient between the first electrode and the second electrode.

11. A display device comprising:

a plurality of pixels;

a scan line;

a signal line;

a first line;

a second line; and

an insulating layer that includes an opening in each of the plurality of pixels,

wherein at least one pixel among the plurality of pixels includes

a selection transistor that includes a gate electrode connected to the scan line, a first source/drain electrode connected to the signal line, and a second source/drain electrode, and

a light-emitting transistor that includes a gate electrode to which a voltage corresponding to a gradation value of the at least one pixel is applied through the second source/drain electrode of the selection transistor, a first electrode connected to the first line, a second electrode connected to the second line, and a channel layer including quantum dots, and controls the quantum dots to emit light by carriers flowing through the channel layer,

the channel layer of the light-emitting transistor is disposed inside the opening of the insulating layer,

the first electrode and the second electrode of the light-emitting transistor are formed on upper sides of the channel layer and the insulating layer, and

the light-emitting transistor includes an auxiliary electrode that is formed on an opposite side to the gate electrode across the channel layer therebetween.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: SATO, TOSHIHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 043118/0569 →
Priority Claims (1)
JP 2015-014573 · Jan 28, 2015 · national
Continuity (2)
Continuation PCTJP2016052029 · Jan 25, 2016
Related Publication 20180012951A1 · Jan 11, 2018