Methods and apparatus for a track and hold amplifier

1. A track-and-hold amplifier circuit configured to be coupled to a supply voltage and a first reference voltage and receive an input signal, comprising:

a gain setting element coupled to the input signal;

a cascode circuit coupled to the gain setting element;

a track-and-hold capacitor comprising:

a first capacitor terminal coupled to the gain setting element at a first node; and

a second capacitor terminal; and

an isolation circuit, coupled to the second capacitor terminal of the track-and-hold capacitor and the cascode circuit, and configured to selectively isolate transient current in the track-and-hold capacitor and redirect the transient current through at least a portion of the cascode circuit,

wherein the isolation circuit comprises:

a third transistor comprising:

a first terminal; and

a second terminal;

wherein:

the first terminal is directly coupled to the second capacitor terminal at a third node; and

the second terminal is directly coupled to the cascode circuit.

2. The track-and-hold amplifier according to claim 1 , further comprising a first current source, wherein the first current source is:

coupled to the cascode circuit and the gain setting element at the first node; and

selectively coupled to the track-and-hold capacitor.

3. The track-and-hold amplifier according to claim 1 , wherein the isolation circuit further comprises:

a second current source coupled to the third node; and

a switch coupled between the second terminal and the first reference voltage.

4. The track-and-hold amplifier according to claim 3 , wherein:

the third transistor further comprises a third terminal coupled to a dynamic voltage;

the second terminal is coupled to the cascode circuit via a fourth node.

5. The track-and-hold amplifier according to claim 3 , wherein the switch selectively couples the second terminal:

to the first reference voltage during a hold phase; and

to the cascode circuit via a fourth node during a track phase.

6. The track-and-hold amplifier according to claim 1 , wherein:

the cascode circuit comprises:

a first transistor; and

a second transistor;

wherein a fourth node is positioned between the first and second transistors; and

the isolation circuit comprises a clamp device coupled to the fourth node and the first reference voltage.

7. The track-and-hold amplifier according to claim 6 , wherein the clamp device has a clamping voltage that is greater than a drain-to-source voltage of the first transistor.

8. The track-and-hold amplifier according to claim 1 , wherein the gain setting element comprises:

a first impedance element coupled in series with a second impedance element; and

a second node positioned between the first and second impedance elements;

wherein:

each impedance element may comprise at least one of a resistor and a capacitor; and

a series capacitance value of the first and second impedance elements is less than a capacitance value of the track-and-hold capacitor.

9. The track-and-hold amplifier according to claim 1 , wherein the cascode circuit is coupled to:

the gain setting element via a second node; and

a bias voltage.

10. The track-and-hold amplifier according to claim 1 , wherein the isolation circuit comprises a clamp device configured to provide a current path from the isolation circuit to the first reference voltage when at least a portion of the cascode circuit is off.

11. The track-and-hold amplifier according to claim 1 , further comprising:

a third current source;

a fourth transistor coupled to the third current source and a second reference voltage; and

a fifth transistor coupled to the third current source, the input signal, and the first reference voltage.

12. A method for improving an output signal settling time for a track-and-hold amplifier, comprising:

during a tracking phase:

supplying a first current to a cascode circuit comprising a first transistor and a second transistor;

tracking an input signal at a first terminal of a track-and-hold capacitor;

supplying a second current to a third transistor coupled to a second terminal of the track-and-hold capacitor; and

directing a transient current through the track-and-hold capacitor to a reference voltage through one of: the first transistor and a clamp device;

during a holding phase:

selectively coupling the third transistor to the reference voltage;

stopping the first current; and

supplying a dynamic voltage to the third transistor.

13. An imaging system, comprising:

a plurality of pixel columns;

a plurality of track-and-hold amplifiers, wherein:

each pixel column is coupled to one track-and-hold amplifier; and

each track-and-hold amplifier comprises:

a gain setting element coupled to the input signal;

a cascode circuit, coupled to the gain setting element at a second node and a bias voltage, comprising:

a first transistor; and

a second transistor;

a track-and-hold capacitor, comprising:

a first terminal; and

a second terminal;

a first current source, coupled to the cascode circuit and the gain setting element at a first node, and selectively coupled to the track-and-hold capacitor;

a third transistor, comprising:

a first terminal;

a second terminal; and

a third terminal;

wherein:

 the first terminal of the third transistor is coupled to the second terminal of the track-and-hold capacitor at a third node;

 the second terminal of the third transistor is coupled to the cascode circuit at a fourth node; and

 the third terminal of the third transistor is coupled to a dynamic voltage;

a switch coupled between the second terminal of the third transistor and a reference voltage; and

a second current source coupled to the third node.

14. The imaging system according to claim 13 , wherein the switch selectively couples the second terminal of the third transistor:

to the reference voltage during a hold phase; and

to the cascode circuit via a fourth node during a track phase.

15. The imaging system according to claim 13 , wherein the gain setting element comprises:

a first impedance element coupled in series with a second impedance element; and

a second node positioned between the first and second impedance elements;

wherein:

each impedance element may comprise at least one of a resistor and a capacitor; and

a series capacitance value of the first and second impedance elements is less than a capacitance value of the track-and-hold capacitor.

16. The imaging system according to claim 13 , further comprising a ramp analog-digital converter (ADC) configured to receive an output signal from each track-and-hold amplifier, and wherein the dynamic voltage is a ramp voltage.

17. The imaging system according to claim 13 , further comprising a clamp device coupled between the fourth node and the reference voltage, wherein the clamp device has a clamping voltage that is greater than a drain-to-source voltage of the first transistor.

18. The imaging system according to claim 13 , further comprising a clamp device configured to provide a current path from the third transistor to the reference voltage when the first transistor is off.

19. The imaging system according to claim 13 , further comprising:

a third current source;

a fourth transistor coupled to the third current source and a reference voltage; and

a fifth transistor coupled to the third current source.