IP Library Granted Patent US 10,164,091
Granted Patent B1
US 10,164,091 · App. 15/666,814 · Granted Dec 25, 2018

Electronic device including a ring suppression structure

Inventor: Gary Horst Loechelt (Tempe, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/7815H01L23/5286H01L27/0635H01L29/0634H01L29/7805
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Quick Facts
Patent No.
US 10,164,091
App. No.
15/666,814
Granted
Dec 25, 2018
Kind
B1
Abstract

A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.

Claims (43)

1. An electronic device comprising:

a substrate including a semiconductor material;

a first trench;

a second trench spaced apart from the first trench; and

a ring suppression structure disposed between the first and second trenches and including a bipolar transistor structure that includes:

a first doped region overlying the substrate and having a first conductivity type;

a second doped region overlying the first doped region and having a second conductivity type opposite that of the first conductivity type; and

a third doped region overlying the second doped region and having the first conductivity type.

2. The electronic device of claim 1 , further comprising a gate electrode of a junction field-effect transistor structure adjacent to the first doped region.

3. The electronic device of claim 2 , wherein the gate electrode is closer to:

a bottom of the first trench than to a top of the first trench;

a bottom of the second trench than to a top of the second trench; or

the bottoms of the first and second trenches than to the tops of the first and second trenches.

4. The electronic device of claim 1 , wherein:

the first doped region includes a first portion, a second portion, and a third portion;

the second portion of the first doped region is disposed between and narrower than each of the first and third portions of the first doped region; and

the second doped region is closer to the third portion of the first doped region than to each of the first and second portions of the first doped region.

5. The electronic device of claim 4 , wherein the second portion of the first doped region includes a pinch-off region of a junction field-effect transistor structure.

6. The electronic device of claim 5 , further comprising a gate electrode of the junction field-effect transistor structure adjacent to the second portion of the first doped region.

7. The electronic device of claim 1 , wherein the second doped region is a base region of the bipolar transistor structure.

8. The electronic device of claim 1 , further comprising an active field-effect transistor structure, wherein the active field-effect transistor structure and the ring suppression structure are disposed between the first and second trenches.

9. The electronic device of claim 7 , wherein the third doped region includes a collector region of the bipolar transistor structure.

10. The electronic device of claim 9 , wherein the first doped region includes an emitter region of the bipolar transistor structure.

11. An electronic device comprising:

a ring suppression structure including:

a first portion of a first doped region having a first conductivity type;

a second doped region overlying the first doped region and having a second conductivity type opposite the first conductivity type; and

a first portion of a third doped region overlying the second doped region and having the first conductivity type; and

a contact structure including:

a second portion of the first doped region; and

a second portion of the third doped region,

wherein the contact structure has a different composition as compared to the ring suppression structure.

12. The electronic device of claim 11 , wherein the second doped region abuts each of the first and third doped regions, is a base region of a bipolar transistor structure, and is coupled to a power supply terminal.

13. The electronic device of claim 11 , further comprising a fourth doped region underlying the first and second portions of the first doped region and having the second conductivity type, wherein the fourth doped regions is coupled to a power supply terminal.

14. The electronic device of claim 13 , wherein:

the first portion of the first doped region includes a drain region of a first junction field-effect transistor and an anode of a first charge storage element; and

the second portion of the first doped region includes a drain region of a second junction field-effect transistor and an anode of a second charge storage element; and

the fourth doped region includes cathodes of the first and second charge storage elements.

15. The electronic device of claim 11 , wherein the ring suppression structure and the contact structure are disposed within a same pillar.

16. The electronic device of claim 15 , wherein from a top view, the contact structure is narrower than the ring suppression structure.

17. The electronic device of claim 15 , wherein each of the ring suppression and contact structures includes a doped semiconductor layer along a sidewall of the pillar.

18. The electronic device of claim 17 , wherein a portion of the doped semiconductor layer includes a drift region of an insulated gate field-effect transistor.

19. The electronic device of claim 11 , wherein the contact structure does not include any portion of the second doped region.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2017
From: LOECHELT, GARY HORST
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043170/0109 →