IP Library Granted Patent US 10,090,757
Granted Patent B2
US 10,090,757 · App. 15/673,011 · Granted Oct 2, 2018

Power factor correction circuit and method

Inventors: Jintae Kim (Sungnam-si, KR); Sangcheol Moon (Bucheon, KR); Hangseok Choi (Suwon, KR)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H02M1/4241H02M1/083H02M7/06H02M2001/0048
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Quick Facts
Patent No.
US 10,090,757
App. No.
15/673,011
Granted
Oct 2, 2018
Kind
B2
Abstract

A Power Factor Correction (PFC) circuit includes an oscillator circuit. The oscillator circuit receives a valley detect signal indicating a zero current condition, determines a blanking time according to an operational cycle of the PFC circuit, and determines to initiate the operational cycle according to the valley detect signal and the blanking time. Determining the blanking time includes selecting one of a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit. The PFC circuit may operate in a Boundary Conduction Mode or a Discontinuous Conduction Mode depending on whether a charge-discharge period is greater than the blanking time. The PFC circuit may determine, according to its output voltage, a first duration of a charging period, determine a delay time according to zero current times of previous operational cycles, and extend the first duration of the charging period by the delay time.

Claims (51)

1. A Power Factor Correction (PFC) circuit, the PFC circuit comprising:

an oscillator circuit to:

receive a valley detect signal indicating a zero current condition;

determine a count N corresponding to a count of operational cycles of the PFC circuit modulo a cardinality of a plurality of predetermined blanking times;

determine a blanking time as being the N th predetermined blanking time of the plurality of predetermined blanking times; and

determine to initiate an operational cycle of the PFC circuit according to the valley detect signal and the blanking time.

2. The PFC circuit of claim 1 , wherein the cardinality of the plurality of predetermined blanking times is two.

3. The PFC circuit of claim 1 ,

wherein the PFC circuit operates in a Boundary Conduction Mode (BCM) when a duration of a charge-discharge period of the operational cycle is greater than the blanking time, and

wherein the PFC circuit operates in a Discontinuous Conduction Mode (DCM) when the duration of a charge-discharge period of the operational cycle is less than the blanking time.

4. The PFC circuit of claim 3 , further comprising:

a first feedback loop circuit to determine, according to an output voltage of the PFC circuit, a first duration of a charging period of the operational cycle; and

a second feedback loop circuit to determine a delay time according to zero current times of one or more previous operational cycles and to extend the first duration of the charging period by the delay time.

5. The PFC circuit of claim 4 , wherein a first control signal is generated by the first feedback loop circuit and has a first pulse that is asserted for a duration corresponding to the first duration, the PFC circuit further comprising:

a turn off delay circuit included in the second feedback loop circuit, the turn off delay circuit to receive the first control signal and to:

assert a second control signal immediately in response to an assertion of the first control signal; and

de-assert the second control signal after the delay time in response to a de-assertion of the first control signal.

6. The PFC circuit of claim 4 , wherein the delay time is zero when the PFC circuit operates in BCM, and is greater than zero when the PFC circuit operates in DCM.

7. The PFC circuit of claim 1 , wherein the oscillator circuit determines to initiate the operational cycle in response to the valley detect signal indicating the zero current condition after a blanking time of an immediately previous operational cycle has expired.

8. The PFC circuit of claim 1 , wherein the blanking time begins at the time the operational cycle is initiated.

9. A method for controlling a PFC circuit, the method comprising:

producing a valley detect signal indicating a zero current condition;

determining a count N corresponding to a count of operational cycles of the PFC circuit modulo a cardinality of a plurality of predetermined blanking times;

selecting a blanking time from the plurality of predetermined blanking times according to the count N; and

determine to initiate an operational cycle of the PFC circuit according to the valley detect signal and the blanking time.

10. The method of claim 9 , wherein the cardinality of the plurality of predetermined blanking times is two.

11. The method of claim 9 , further comprising:

operating the PFC circuit in a Boundary Conduction Mode (BCM) when a duration of a charge-discharge period of the operational cycle is greater than the blanking time, and

operating the PFC circuit in a Discontinuous Conduction Mode (DCM) when the duration of a charge-discharge period of the operational cycle is less than the blanking time.

12. The method of claim 11 , further comprising:

determining, according to an output voltage of the PFC circuit, a first duration of a charging operation of the operational cycle;

determining a delay time according to zero current times of one or more previous operational cycles; and

extending the first duration of the charging operation by the delay time.

13. The method of claim 12 , further comprising:

generating a first control signal having a first pulse that is asserted for a duration corresponding to the first duration;

asserting a second control signal immediately in response to an assertion of the first control signal;

de-assert the second control signal after the delay time in response to a de-assertion of the first control signal; and

performing the charging operation when the second control signal is asserted.

14. The method of claim 12 , wherein the delay time is zero when the PFC circuit operates in BCM, and is greater than zero when the PFC circuit operates in DCM.

15. The method of claim 9 , further comprising:

determining to initiate the operational cycle in response to the valley detect signal indicating the zero current condition after a blanking time of an immediately previous operational cycle has expired.

16. The method of claim 9 , wherein the blanking time begins at the time the operational cycle is initiated.

17. A Power Factor Correction (PFC) circuit, the PFC circuit comprising:

a current sense circuit to generate a current sense signal according to a sensed current;

a zero current detector circuit to generate a valley detect signal using the current sense signal;

an oscillator circuit to receive the valley detect signal, select a blanking time from among a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit, and generate an on trigger signal according to the valley detect signal and the blanking time; and

a first feedback circuit to determine a first duration of a gate control signal according to an output voltage of the PFC circuit,

wherein the PFC circuit initiates a charging operation in response to an assertion of the on trigger signal, and terminates the charging operation after the first duration has elapsed after initiating the charging operation.

18. The PFC circuit of claim 17 , further comprising:

a second feedback circuit to determine a delay time according to a duty cycle of the sensed current,

wherein the PFC circuit terminates the charging operation after a second duration has elapsed after initiating the charging operation, the second duration being equal to the first duration plus the delay time.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2017
From: KIM, JINTAE; MOON, SANGCHEOL; CHOI, HANGSEOK
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 043612/0605 →
Continuity (2)
Provisional Application 62377292 · Aug 19, 2016
Related Publication 20180054113A1 · Feb 22, 2018
Cited By (1)
US 12,413,143