Method and apparatus for sorting elements in hardware structures

1. A method for sorting elements in an ordered retirement queue, the method comprising:

selecting a plurality of elements to order from an unordered input queue (UIQ) of a register file of a processor;

presenting each element of the plurality of elements to a multiplexer, wherein the multiplexer outputs to a port of the ordered retirement queue;

determining a match between a port number of the port and at least one least significant bit of an identifier of an element in the plurality of elements; and

generating a select signal for the multiplexer corresponding to the element in the plurality of elements.

2. The method of claim 1 , further comprising:

forwarding a packet corresponding to the element of the plurality of elements to the port of the ordered retirement queue from the UIQ using the multiplexer.

3. A non-transitory machine-readable medium that stores instructions, which when executed by a processor of a computing device, cause the computing device to:

select a plurality of elements to order from an unordered input queue (UIQ) of a register file of the processor;

present each element of the plurality of elements to a multiplexer, wherein the multiplexer outputs to a port of an ordered retirement queue;

determine a match between a port number of the port and at least one least significant bit of an identifier of an element in the plurality of elements; and

generate a select signal for the multiplexer corresponding to the element in the plurality of elements.

4. The non-transitory machine-readable medium of claim 3 , wherein the selecting comprises:

selecting elements within a range in response to finding a match between at least one most significant bit of the range and corresponding bits of a respective identifier operable to tag each of the plurality of elements.

5. The non-transitory machine-readable medium of claim 4 , wherein the selecting and the generating are performed in response to a communication protocol controlled by a reorder buffer in a pipeline of the processor, and wherein the communication protocol communicates the range and a number of elements to be ordered to the register file.

6. The non-transitory machine-readable medium of claim 5 , wherein the communication protocol indicates a number of elements to be retired during a clock cycle from the ordered retirement queue.

7. The non-transitory machine-readable medium of claim 3 , wherein the instructions further cause the computing device to:

forward a packet corresponding to the element of the plurality of elements to the port of the ordered retirement queue from the UIQ using the multiplexer.

8. The non-transitory machine-readable medium of claim 7 , wherein the determining determines a match using port content address match (CAM) circuitry, wherein the select signal is generated in response to the CAM circuitry indicating a match.

9. The non-transitory machine-readable medium of claim 8 , wherein a write enable signal is generated for the port by performing a logical OR of the select signal.

10. The non-transitory machine-readable medium of claim 3 , wherein the instructions further cause the computing device to:

write the packet into the port of the ordered retirement queue.

11. The non-transitory machine-readable medium of claim 3 , wherein the ordered queue comprises elements to be retired from the register file in a retirement cycle of a pipeline of the processor.

12. An apparatus for sorting elements stored in hardware structures, said apparatus comprising:

a memory;

a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to:

select a plurality of elements to order from an unordered input queue (UIQ);

present each element of the plurality of elements to a multiplexer, wherein the multiplexer outputs to a port of an ordered retirement queue;

determine a match between a port number of the port and at least one least significant bit of an identifier of an element in the plurality of elements; and

generate a select signal for the multiplexer corresponding to the element in the plurality of elements.

13. The apparatus of claim 12 , wherein said processor is further configured to:

forward a packet corresponding to the element of the plurality of elements to the port of the ordered retirement queue from the UIQ using the multiplexer.

14. The apparatus of claim 13 , wherein the determining determines a match using port content address match (CAM) circuitry, wherein the select signal is generated in response to the CAM circuitry indicating a match.

15. The apparatus of claim 14 , wherein a write enable signal is generated for the port by performing a logical OR of the select signal.

16. The apparatus of claim 12 , wherein said processor is further configured to:

write the packet into the port of the ordered retirement queue.

17. The apparatus of claim 12 , wherein the selecting comprises:

selecting elements within a range in response to finding a match between at least one most significant bit of the range and corresponding bits of a respective identifier operable to tag each of the plurality of elements.

18. The apparatus of claim 17 , wherein the selecting and the generating are performed in response to a communication protocol controlled by a reorder buffer in a pipeline of the processor, and wherein the communication protocol communicates the range and a number of elements to be ordered to the register file.

19. The apparatus of claim 18 , wherein the communication protocol indicates a number of elements to be retired during a clock cycle from the ordered retirement queue.

20. The apparatus of claim 12 , wherein the ordered retirement queue comprises elements to be retired from the register file in a retirement cycle of a pipeline of the processor.