Two-step self-test circuit for microcontroller unit and antenna
A system is disclosed. The system includes an antenna and a processor. The processor has at least four ports: a first input port coupled to a first portion of the continuity component; a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor; a second output port coupled through a third resistor to the first portion of the antenna; and a second input port coupled to a second portion of the antenna and through a fourth resistor to ground. The processor is operable to activate and deactivate the appropriate ports to put the processor in one of three operating modes: an AC detection mode, an AC self-test mode, and a continuity test mode.
1. A system, comprising:
an antenna having a first portion and a second portion; and
a processor having:
a first input port coupled to the first portion of the antenna;
a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor;
a second output port coupled through a third resistor to the first portion of the antenna; and
a second input port coupled to the second portion of the antenna and through a fourth resistor to ground, wherein when the processor is in an AC self-test mode, the first input port and the first output port are both active, while the second output port and the second input port are both inactive, wherein when the processor is in a continuity test mode, the first input port and the first output port are both inactive, while the second output port and the second input port are both active, and wherein in the continuity test mode a test signal is injected through the antenna.
2. The system of claim 1 , wherein when the processor is in an AC detection mode, the first input port is active and the first output port, second output port, and second input port are inactive.
3. The system of claim 1 , wherein in the AC self-test mode, an alternating voltage is placed on the first output port.
4. The system of claim 3 , wherein the first input port detects the presence of the alternating voltage.
5. The system of claim 3 , wherein when the first input port fails to detect the presence of an alternating voltage a self-test failure is indicated.
6. The system of claim 1 , wherein in the continuity mode, a voltage is placed on the second output port.
7. The system of claim 6 , wherein a portion of the voltage is detected at the second input port.
8. The system of claim 6 , wherein when an incorrect portion of the voltage is detected at the second input port a continuity test failure is indicated.
9. A method of testing an antenna, comprising:
in a first mode, injecting an AC signal from a first output port of a processor into circuitry at a first portion of the antenna and detecting the presence of the AC signal at a first input port of the processor, wherein the first input port is coupled to the first portion of the antenna, wherein the first output port is coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor, and wherein when the processor is in an AC self-test mode, the first input port and the first output port are both active, while the second output port and the second input port are both inactive; and
in a second mode, injecting a voltage from a second output port of the processor through the first portion of the antenna and detecting the presence of the voltage on a second portion of the antenna at a second input port of the processor, wherein the second output port is coupled through a third resistor to a second portion of the antenna, wherein the second input port is coupled to the first portion of the antenna and through a fourth resistor to ground, wherein when the processor is in a continuity test mode, the first input port and the first output port are both inactive, while the second output port and the second input port are both active, and wherein in the continuity test mode a test signal is injected through the antenna.
10. The method of claim 9 , further comprising in the first mode, when the AC signal is not detected at the first input port, providing an indication that an AC self-test has failed.
11. The method of claim 9 , further comprising in the second mode, when a portion of the voltage received at the second input port does not equal an expected voltage, providing an indication that a continuity test has failed.
12. A system, comprising:
an antenna having a first portion and a second portion; and
a processor having:
a first input port coupled to the first portion of the antenna;
a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor;
a second output port coupled through a third resistor to a second portion of the antenna; and
a second input port coupled to the first portion of the antenna and through a fourth resistor to ground, wherein when the processor is in an AC self-test mode, the first input port and the first output port are both active, while the second output port and the second input port are both inactive, and wherein when the processor is in a continuity test mode, the first input port and the first output port are both inactive, while the second output port and the second input port are both active, wherein in the continuity test mode a test signal is injected through the antenna.
13. The system of claim 12 , wherein in the AC self-test mode an alternating voltage is placed on the first output port.
14. The system of claim 13 , wherein the first input port detects the presence of the alternating voltage.
15. The system of claim 14 , wherein when the first input port fails to detect the presence of an alternating voltage a self-test failure is indicated.
16. The system of claim 12 , wherein in the continuity test mode a voltage is placed on the second output port.
17. The system of claim 16 , wherein a portion of the voltage is detected at the second input port.
18. The system of claim 17 , wherein when an incorrect portion of the voltage is detected at the second input port a continuity test failure is indicated.