Double balanced mixer
A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.
1. A double balanced mixer fabricated as an integrated circuit and configured to be coupled to both (1) a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and (2) a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, the double balanced mixer including:
a four-node ring including four branches, each branch including at least one low threshold voltage field effect transistor (FET) having a close-to-zero turn-on voltage, each FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode,
wherein a first pair of opposing nodes of the four-node FET ring are configured to be connected to the pair of ports on the balanced side of the first balun, and a second pair of opposing nodes of the four-node FET ring are configured to be connected through corresponding capacitors to the pair of ports on the balanced side of the second balun.
2. The double balanced mixer of claim 1 , wherein an IF signal port is coupled to the second pair of opposing nodes of the four-node FET ring through isolating circuitry.
3. The double balanced mixer of claim 2 , wherein the isolating circuitry includes phase-shifting circuitry.
4. The double balanced mixer of claim 3 , wherein signals from the two nodes of the FET ring coupled to the IF signal port are phase shifted by the phase-shifting circuitry such that the signals are in-phase.
5. The double balanced mixer of claim 2 , wherein the isolating circuitry includes quarter-wave isolation elements.
6. The double balanced mixer of claim 1 , wherein the four-node FET ring includes at least two FETs per branch.
7. The double balanced mixer of claim 1 , wherein the four-node FET ring includes at least four FETs per branch.
8. The double balanced mixer of claim 1 wherein the turn-on voltage of the low threshold voltage FETs is approximately equal to a threshold voltage of the low threshold voltage FETs.
9. The double balanced mixer of claim 1 , wherein the integrated circuit is fabricated using one of thin film, partially depleted, or fully depleted CMOS technology on a silicon-on-insulator (SOI) or a silicon-on-sapphire (SOS) substrate.
10. The double balanced mixer of claim 1 , wherein at least one of the first balun and the second balun is fabricated on the integrated circuit and coupled to the double balanced mixer.
11. A method for fabricating a double balanced mixer as an integrated circuit configured to be coupled to both (1) a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and (2) a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, the method including:
(a) providing a four-node ring including four branches, each branch including at least one low threshold voltage field effect transistor (FET) having a close-to-zero turn-on voltage, each FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode,
(b) configuring a first pair of opposing nodes of the four-node FET ring to be connected to the pair of ports on the balanced side of the first balun; and
(c) configuring a second pair of opposing nodes of the four-node FET ring to be connected through corresponding capacitors to the pair of ports on the balanced side of the second balun.
12. The method of claim 11 , further including coupling an IF signal port to the second pair of opposing nodes of the four-node FET ring through isolating circuitry.
13. The method of claim 12 , wherein the isolating circuitry includes phase-shifting circuitry.
14. The method of claim 13 , further including phase shifting signals from the two nodes of the FET ring coupled to the IF signal port such that the signals are in-phase.
15. The method of claim 12 , wherein the isolating circuitry includes quarter-wave isolation elements.
16. The method of claim 11 , wherein the four-node FET ring includes at least two FETs per branch.
17. The method of claim 11 , wherein the four-node FET ring includes at least four FETs per branch.
18. The method of claim 11 , wherein the turn-on voltage of the low threshold voltage FETs is approximately equal to a threshold voltage of the low threshold voltage FETs.
19. The method of claim 11 , further including fabricating the integrated circuit using one of thin film, partially depleted, or fully depleted CMOS technology on a silicon-on-insulator (SOI) or a silicon-on-sapphire (SOS) substrate.
20. The method of claim 11 , further including fabricating at least one of the first balun and the second balun on the integrated circuit and coupled to the double balanced mixer.
21. The method of claim 11 , wherein the turn-on voltage of the low threshold voltage FETs is in the range of about ±0.1V.
22. The double balanced mixer of claim 1 , wherein the turn-on voltage of the low threshold voltage FETs is in the range of about ±0.1V.