Semiconductor memory device
View Patent ↗According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
1. A semiconductor memory device comprising:
a first memory cell string including memory cells coupled in series;
a second memory cell string including memory cells coupled in series;
a word line electrically coupled to a first memory cell in the first memory cell string and a second memory cell in the second memory cell string;
a first selection transistor including first and second terminals, the first terminal being electrically coupled to a first end of the first memory cell string;
a second selection transistor including third and fourth terminals and being a depression type, the third terminal being electrically coupled to a second end of the first memory cell string;
a third selection transistor including fifth and sixth terminals and being an enhancement type, the fifth terminal being electrically coupled to the fourth terminal of the second selection transistor;
a fourth selection transistor including seventh and eighth terminals, the seventh terminal being electrically coupled to a first end of the second memory cell string;
a fifth selection transistor including ninth and tenth terminals and being an enhancement type, the ninth terminal being electrically coupled to a second end of the second memory cell string; and
a sixth selection transistor including eleventh and twelve terminals and being a depression type, the eleventh terminal being electrically coupled to the tenth terminal of the fifth selection transistor.
2. The semiconductor memory device according to claim 1 , further comprising:
a first selection line electrically coupled to gates of the second and fifth selection transistors; and
a second selection line electrically coupled to gates of the third and sixth selection transistors,
wherein a first voltage is applied to the first selection line and a second voltage is applied to the second selection line.
3. The semiconductor memory device according to claim 2 , farther comprising:
a third selection line electrically coupled to a gate of the first selection transistor; and
a fourth selection line electrically coupled to a gate of the fourth selection transistor.
4. The semiconductor memory device according to claim 1 , further comprising:
a bit line electrically coupled to the second and eighth terminals; and
a source line electrically coupled to the sixth and twelve terminals.
5. The semiconductor memory device according to claim 2 , wherein in a case of selecting the first memory cell string, an L-level voltage that turns on the D-type of the second selection transistor and turns off on the E-type of the fifth selection transistor is applied to the first selection line, and an H-level voltage that turns on both the D-type and the E-type is applied to the second selection line, thereby selecting the first memory cell string alone.
6. The semiconductor memory device according to claim 2 , wherein in a case of selecting the second memory cell string, an L-level voltage that turns on the D-type of the sixth selection transistor and turns off on the E-type of the third selection transistor is applied to the second selection line, and an H-level voltage that turns on both the D-type and the E-type is applied to the first selection line, thereby selecting the second memory cell string alone.
7. The semiconductor memory device according to claim 1 , further comprising a control circuit configured to receive a first data of n bits and write the first data into the first memory cell in a first program sequence, and receive a second data and write the first data into the first memory cell by using the second data in a second program sequence.
8. The semiconductor memory device according to claim 7 ,
wherein the second data is generated from the first data.
9. The semiconductor memory device according to claim 8 ,
wherein the second data is acquired by executing an arithmetic operation of exclusive NOR with respect to the first data.
10. The semiconductor memory device according to claim 7 ,
wherein the second program sequence is executed after a write operation is executed to a third memory cell adjacent to the first memory cell.
11. The semiconductor memory device according to claim 7 ,
wherein the first and second program sequences include read voltages, and kinds of read voltages in the first program sequence are fewer than kinds of read voltages in the second program sequence.
12. The semiconductor memory device according to claim 7 ,
wherein the second program sequence includes a reading by a first read voltage and a reading by a second read voltage different from the first read voltage with respect to the first memory cell.
13. The semiconductor memory device according to claim 11 ,
wherein the read voltages used for write verify of the first memory cell in the first program sequence are A, B, and C to satisfy (A<B<C), and the read voltages in the second program sequence include E (B<E<C) and A.
14. The semiconductor memory device according to claim 13 ,
wherein the control circuit applies a first write voltage to the first memory cell after the reading is executed by the read voltages E and A in the second program sequence, the first write voltage is greater than the read voltages E and A.
15. The semiconductor memory device according to claim 11 ,
wherein the read voltages used for write verify of the first memory cell in the first program sequence are A, B, and C and satisfy (A<B<C), the read voltages in the second program sequence include E (B<E<C) and A, D (A<D<B) and B, and E (B<E<C) and C.
16. The semiconductor memory device according to claim 15 ,
wherein the control circuit applies a first write voltage to the first memory cell, after a reading is executed by the read voltages E and A in the second program sequence, applies a second write voltage to the first memory cell, after a reading is executed by the read voltages D and B in the second program sequence, and applies a third write voltage to the first memory cell, after a reading is executed by the read voltages E and C in the second program sequence.
17. The semiconductor memory device according to claim 7 ,
further comprising memory cells which include the first and second memory cells,
wherein the memory cells are arranged three-dimensionally on a semiconductor substrate.
18. The semiconductor memory device according to claim 7 ,
wherein the control circuit is controlled by at least one of control signals Address Latch Enable (ALE), Command Latch Enable (CLE), Write Enable (WE), and Read Enable (RE).
19. The semiconductor memory device according to claim 7 ,
wherein after end of the second program sequence, the first program sequence is again executed.
20. The semiconductor memory device according to claim 7 ,
wherein in the second program sequence, the control circuit reads data stored in the first memory cell,
restores the first data based on the data read from the first memory cell and the second data, and
writes the restored first data into the first memory cell.
21. The semiconductor memory device according to claim 7 ,
further comprising a data circuit configured to receive the first data to be written into the first memory cell in the first program sequence and to receive the second data in the second program sequence.