Real-time interleaved multi-scan-out

1. A display device comprising:

a two-dimensional pixel array comprising a first region and a second region, each region including two or more lines of pixels; and

a control circuit configured to:

select a first one or more lines of pixels in the first region to receive image data for an image frame; and

select, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region to receive the image data for the image frame, a first one or more lines of pixels in the second region to receive the image data for the image frame.

2. The display device of claim 1 , wherein:

the first one or more lines of pixels in the first region consists of a single line of pixels; and

the first one or more lines of pixels in the second region consists of a single line of pixels.

3. The display device of claim 1 , wherein:

the first region of the two-dimensional pixel array is configured to display images to one eye of a user; and

the second region of the two-dimensional pixel array is configured to display images to another eye of the user.

4. The display device of claim 1 , wherein the control circuit comprises a first group of gates and a second group of gates, wherein:

each gate comprises:

a clock input;

a trigger input; and

an output coupled to a respective line of pixels in the first region or the second region;

the outputs of the first group of gates are coupled to the two or more lines of pixels in the first region; and

the outputs of the second group of gates are coupled to the two or more lines of pixels in the second region.

5. The display device of claim 4 , wherein:

the clock inputs of the first group of gates are coupled to a first clock line; and

the clock inputs of the second group of gates are coupled to a second clock line.

6. The display device of claim 4 , wherein:

in the first group of gates,

the trigger input of a first gate in the first group of gates is coupled to a first trigger line for receiving a first trigger signal; and

the output of each gate other than a last gate in the first group of gates is coupled to the trigger input of a next gate in the first group of gates; and

in the second group of gates,

the trigger input of a first gate in the second group of gates is coupled to a second trigger line for receiving a second trigger signal; and

the output of each gate other than a last gate in the second group of gates is coupled to the trigger input of a next gate in the second group of gates.

7. The display device of claim 6 , wherein:

the first trigger signal includes a first pulse;

the second trigger signal includes a second pulse; and

the second pulse is later than the first pulse.

8. The display device of claim 6 , wherein:

the trigger input of the first gate in the second group of gates is coupled to the second trigger line through a switch, the switch configured to selectively couple the trigger input of the first gate in the second group of gates to the second trigger line or to the output of the last gate in the first group of gates.

9. The display device of claim 6 , further comprising a driver circuit configured to provide:

the first trigger signal;

the second trigger signal; and

one or more clock signals for driving the clock inputs of the first group of gates and the clock inputs of the second group of gates.

10. The display device of claim 9 , wherein the driver circuit is further configured to concurrently provide the image data to pixels in a line of pixels of the first one or more lines of pixels in the first region.

11. The display device of claim 10 , wherein the driver circuit is further configured to provide scrambled image data for an image frame to the two-dimensional pixel array.

12. The display device of claim 9 , wherein the driver circuit is further configured to provide a backlight control signal for the two-dimensional pixel array.

13. A control circuit for a two-dimensional pixel array, the control circuit comprising:

a first group of gates; and

a second group of gates,

wherein the two-dimensional pixel array comprises a first region and a second region, each region including two or more lines of pixels; and

wherein the control circuit is configured to:

select, using the first group of gates, a first one or more lines of pixels in the first region to receive image data for an image frame; and

select, using the second group of gates, a first one or more lines of pixels in the second region to receive the image data for the image frame, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region using the first group of gates to receive the image data for the image frame.

14. The control circuit of claim 13 , wherein each gate in the first group of gates and the second group of gates comprises:

a clock input;

a trigger input; and

an output coupled to a respective line of pixels in the first region or the second region.

15. The control circuit of claim 14 , wherein:

in the first group of gates,

the trigger input of a first gate in the first group of gates is coupled to a first trigger line for receiving a first trigger signal; and

the output of each gate other than a last gate in the first group of gates is coupled to the trigger input of a next gate in the first group of gates; and

in the second group of gates,

the trigger input of a first gate in the second group of gates is coupled to a second trigger line for receiving a second trigger signal; and

the output of each gate other than a last gate in the second group of gates is coupled to the trigger input of a next gate in the second group of gates.

16. The control circuit of claim 15 , wherein:

the trigger input of the first gate in the second group of gates is coupled to the second trigger line through a switch; and

the switch is configured to selectively couple the trigger input of the first gate in the second group of gates to the second trigger line or the output of the last gate in the first group of gates.

17. A method for single-panel image display, the method comprising:

selecting, from a two-dimensional pixel array that comprises a first region and a second region each comprising two or more lines of pixels, a first one or more lines of pixels in the first region to receive image data for an image frame; and

selecting, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region to receive the image data for the image frame, a first one or more lines of pixels in the second region to receive the image data for the image frame.

18. The method of claim 17 , wherein:

selecting the first one or more lines of pixels in the first region includes selecting two or more lines of pixels in the first region; and

selecting the first one or more lines of pixels in the second region includes selecting two or more lines of pixels in the second region.

19. The method of claim 17 , wherein:

selecting the first one or more lines of pixels in the first region includes selecting the first one or more lines of pixels in the first region using a first trigger signal; and

selecting the first one or more lines of pixels in the second region includes selecting the first one or more lines of pixels in the second region using a second trigger signal, wherein a phase of the second trigger signal is different from a phase of the first trigger signal.

20. The method of claim 17 , further comprising:

providing, concurrently, the image data to pixels in a line of pixels of the first one or more lines of pixels in the first region.