IP Library Granted Patent US 10,319,639
Granted Patent B2
US 10,319,639 · App. 15/679,664 · Granted Jun 11, 2019

Thin semiconductor package and related methods

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Quick Facts
Patent No.
US 10,319,639
App. No.
15/679,664
Granted
Jun 11, 2019
Kind
B2
Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Claims (26)

1. A method of forming a semiconductor package comprising:

forming a plurality of notches into a first side of a wafer, the first side of the wafer comprising a plurality of electrical contacts;

coating the first side of the wafer and an interior of the plurality of notches with a molding compound;

grinding a second side of the wafer to thin the wafer to a desired thickness;

forming a back metal on a second side of the wafer;

exposing the plurality of electrical contacts through grinding a first side of the molding compound; and

singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

2. The method of claim 1 , further comprising forming a groove through the back metal on the second side of the wafer, coating the second side of the wafer and the back metal with a second molding compound, and grinding the second molding compound to a desired thickness.

3. The method of claim 1 , wherein the plurality of notches are formed using an etching technique.

4. The method of claim 1 , wherein each notch in the plurality of notches is a stepwise notch.

5. The method of claim 1 , wherein the second side is ground to a depth of the plurality of notches.

6. The method of claim 1 , wherein a portion of the wafer separates the back metal and the plurality of notches.

7. The method of claim 1 , wherein the first molding compound is applied using one of a liquid dispensing method, a transfer molding method, and a compression molding method.

8. The method of claim 1 , wherein substantially 90 percent of a back portion of the wafer is removed during grinding the second side of the wafer.

9. The method of claim 1 , wherein the first molding compound is cured between 100 and 200 degrees Celsius with a pressure of substantially 5 psi applied to the second side of the wafer.

10. A method of forming a semiconductor package comprising:

forming a plurality of notches into a second side of a wafer opposite a first side of a wafer, the first side of the wafer comprising a plurality of electrical contacts;

coating the first side of the wafer with a first molding compound;

coating the second side of the wafer with a second molding compound;

grinding the second molding compound to a desired thickness;

forming a metal layer over the second molding compound and the second side of the wafer;

exposing the plurality of electrical contacts through grinding a first side of the first molding compound; and

singulating the wafer along the plurality of notches forming a plurality of semiconductor packages.

11. The method of claim 10 , wherein the plurality of notches are formed using an etching technique.

12. The method of claim 10 , wherein the first molding compound is applied using one of a liquid dispensing method, a transfer molding method, and a compression molding method.

13. The method of claim 10 , wherein the first molding compound and the second molding compound are ground using one of a mechanical polishing and a chemical etching technique.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2017
From: KRISHNAN, SHUTESH; WANG, SW; CHEW, CH; LIEW, HOW KIAT; TAN, FUI FUI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043322/0071 →
Cited By (3)
US 12,374,554 US 12,374,555 US 12,444,609