Device and method for skew compensation between data signal and clock signal

1. A semiconductor device, comprising:

a first buffer configured to output a reception data signal corresponding to a received external data signal;

a second buffer configured to output a reception clock signal corresponding to a received external clock signal;

a latch circuit configured to latch, responsive to the reception clock signal, the reception data signal or a signal generated from the reception data signal to output reception data corresponding to the reception data signal;

a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal; and

a delay control circuitry configured to, in a first calibration process:

responsive to increasing the set delay time from an initial value, determine a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value;

compare an average of the first delay time and the third delay time with a previous optimum value; and

determine an optimum value of the set delay time as one of:

when the average is longer than the previous optimum value, a delay time that is longer than the previous optimum value by a predetermined time duration; and

when the average is shorter than the previous optimum value, a delay time that is shorter than the previous optimum value by a predetermined time duration.

2. The semiconductor device, according to claim 1 , wherein the delay control circuitry is further configured to increase the set delay time from the initial value with first increments, and to increase the set delay time from the first delay time with second increments larger than the first increments.

3. A semiconductor device comprising:

a first buffer configured to output a reception data signal corresponding to a received external data signal;

a second buffer configured to output a reception clock signal corresponding to a received external clock signal;

an inverter configured to generate an inverted clock signal by inverting the reception clock signal;

a selector circuit configured to supply an internal clock signal selected from the reception clock signal and the inverted clock signal;

a latch circuit configured to latch the reception data signal in response to the internal clock signal, wherein the latch circuit outputs reception data corresponding to the reception data signal;

a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal; and

a delay control circuitry configured to:

responsive to increasing the set delay time from an initial value, determine a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value; and

determine an optimum value of the set delay time based on the first delay time and the third delay time,

wherein the selector circuit is further configured to, when the latch circuit latches the first value while the set delay time is the initial value, select the inverted clock signal for determining the first delay time, the second delay time, and the third delay time.

4. A semiconductor device comprising:

a first buffer configured to output a reception data signal corresponding to a received external data signal;

a second buffer configured to output a reception clock signal corresponding to a received external clock signal;

an inverter configured to generate an inverted data signal by inverting the reception data signal; and

a selector circuit configured to supply a selected data signal selected from the reception data signal and the inverted data signal;

a latch circuit configured to latch the selected data signal, wherein the latch circuit outputs reception data corresponding to the selected data signal;

a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal; and

a delay control circuitry configured to:

responsive to increasing the set delay time from an initial value, determine a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value; and

determine an optimum value of the set delay time based on the first delay time and the third delay time,

wherein the selector circuit is further configured to, when the latch circuit latches the first value while the set delay time is the initial value, select the inverted data signal for determining the first delay time, the second delay time, and the third delay time.

5. The semiconductor device according to claim 1 , wherein the previous optimum value of the set delay time is determined in a previous calibration process.

6. The semiconductor device according to claim 1 , wherein the delay control circuitry is further configured to, in a second calibration process performed after the first calibration process:

set the set delay time to the initial value;

responsive to increasing the set delay time from the initial value, determine a fourth delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value; and

determine the optimum value of the set delay time by adding, to the fourth delay time, a half of a difference obtained by subtracting the first delay time from the third delay time.

7. The semiconductor device according to claim 1 , wherein the external data signal and the external clock signal are received in a period between determining the first delay time and determining the second delay time, and

wherein the delay control circuitry is further configured to:

determine, while determining the second delay time, whether the value of the reception data is stabilized to the first value when the first delay time is set as the set delay time, and

adjust the first delay time when the value of the reception data is not stabilized to the first value when the first delay time is set as the set delay time.

8. The semiconductor device according to claim 1 , wherein the external data signal and the external clock signal are received in a period between determining the second delay time and determining the third delay time, and

wherein the delay control circuitry is further configured to:

determine, while determining the third delay time, whether the value of the reception data is stabilized to the second value when the second delay time is set as the set delay time, and

adjust the second delay time when the value of the reception data is not stabilized to the second value when the second delay time is set as the set delay time.

9. A data transfer system, comprising:

a data transmitter configured to output an external data signal and an external clock signal; and

a data receiver configured to:

receive the external data signal via a data transmission line; and

receive the external clock signal via a separate clock transmission line,

wherein the data receiver includes:

a first buffer configured to output a reception data signal corresponding to the external data signal;

a second buffer configured to output a reception clock signal corresponding to the external clock signal;

a latch circuit configured to latch, responsive to the reception clock signal, the reception data signal or a signal generated from the reception data signal to output reception data corresponding to the reception data signal;

a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal; and

a delay control circuitry configured to:

responsive to increasing the set delay time from an initial value, determine a first delay time as a value of the set delay time at which the value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay value at which the value of the reception data is stabilized to the first value;

compare an average of the first delay time and the third delay time with a previous optimum value; and

determine an optimum value of the set delay time as one of:

when the average is longer than the previous optimum value, a delay time that is longer than the previous optimum value by a predetermined time duration; and

when the average is shorter than the previous optimum value, a delay time that is shorter than the previous optimum value by a predetermined time duration.

10. The data transfer system according to claim 9 , wherein data transfer is performed in a period between determining the first delay time and determining the second delay time by transmitting the external data signal and the external clock signal from the data transmitter to the data receiver.

11. The data transfer system according to claim 10 , wherein the delay control circuitry is further configured to:

determine, while determining the second delay time, whether the value of the reception data is stabilized to the first value when the first delay time is set as the set delay time, and

adjust the first delay time when the value of the reception data is not stabilized to the first value when the first delay time is set as the set delay time.

12. The data transfer system according to claim 9 , wherein data transfer is performed in a period between determining the second delay time and determining the third delay time by transmitting the external data signal and the external clock signal from the data transmitter to the data receiver.

13. The data transfer system according to claim 12 , wherein the delay control circuitry is further configured to:

determine, while determining the third delay time, whether the value of the reception data is stabilized to the second value when the second delay time is set as the set delay time, and

adjust the second delay time when the value of the reception data is not stabilized to the second value when the second delay time is set as the set delay time.

14. A method of operating a semiconductor device, the semiconductor device comprising: a first buffer configured to output a reception data signal corresponding to a received external data signal; a second buffer configured to output a reception clock signal corresponding to a received external clock signal; a latch circuit configured to latch, responsive to the reception clock signal, the reception data signal or a signal generated from the reception data signal to output reception data corresponding to the reception data signal; and a delay circuitry configured to delay, by a set delay time, one of the reception data signal and the reception clock signal with respect to the other of the reception data signal and the reception clock signal, the method comprising:

performing a calibration process to determine an optimum value of the set delay time, wherein the calibration process includes:

responsive to increasing the set delay time from an initial value, determining a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determining a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determining a third delay time as a value of the set delay value at which the value of the reception data is stabilized to the first value;

comparing an average of the first delay time and the third delay time with a previous optimum value; and

determining an optimum value of the set delay time as one of:

when the average is longer than the previous optimum value, a delay time that is longer than the previous optimum value by a predetermined time duration; and

when the average is shorter than the previous optimum value, a delay time that is shorter than the previous optimum value by a predetermined time duration.

15. The method according to claim 14 , further comprising:

receiving the external data signal and the external clock signal in a period between determining the first delay time and determining the second delay time.

16. The method according to claim 15 , further comprising:

determining, while determining the second delay time, whether the value of the reception data is stabilized to the first value when the first delay time is set as the set delay time, and

adjusting the first delay time when the value of the reception data is not stabilized to the first value when the first delay time is set as the set delay time.

17. The method according to claim 14 , further comprising:

receiving the external data signal and the external clock signal in a period between determining the second delay time and determining the third delay time.

18. The method according to claim 17 , further comprising:

determining, while determining the third delay time, whether the value of the reception data is stabilized to the second value when the second delay time is set as the set delay time, and

adjusting the second delay time when the value of the reception data is not stabilized to the second value when the second delay time is set as the set delay time.

19. A data transfer system, comprising:

a data transmitter configured to output an external data signal and an external clock signal; and

a data receiver configured to:

receive the external data signal via a data transmission line; and

receive the external clock signal via a separate clock transmission line, wherein the data receiver includes:

a first buffer configured to output a reception data signal corresponding to an external data signal;

a second buffer configured to output a reception clock signal corresponding to the external clock signal;

an inverter configured to generate one of the following: (i) an inverted data signal corresponding to the reception data signal, and (ii) an inverted clock signal corresponding to the reception clock signal;

a latch circuit configured to latch one of the reception data signal and the inverted data signal in response to one of the reception clock signal and the inverted clock signal, wherein the latch circuit outputs reception data corresponding to the reception data signal;

a delay control circuitry configured to:

responsive to increasing a set delay time from an initial value, determine a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value; and

determine an optimum value of the set delay time based on the first delay time and the third delay time, and

a delay circuitry configured to delay, by the optimum value, one of (i) the reception data signal and (ii) the reception clock signal with respect to the other of (i) and (ii),

wherein, when the latch circuit latches the first value while the set delay time, is the initial value, the latch circuit uses one of the inverted data signal and the inverted clock signal for determining the first delay time, determining the second delay time, and determining the third delay time.

20. A method comprising:

outputting a reception data signal from a first buffer;

outputting a reception clock signal from a second buffer;

inverting one of the reception data signal and the reception clock signal;

latching, using a latch circuit, one of the reception data signal and the inverted reception data signal responsive to one of the reception clock signal and the inverted reception clock signal, wherein the latch circuit outputs reception data corresponding to the reception data signal;

responsive to increasing a set delay time from an initial value, determining a first delay time as a value of the set delay time at which a value of the reception data is stabilized to a first value;

responsive to increasing the set delay time from the first delay time, determine a second delay time as a value of the set delay time at which the value of the reception data is stabilized to a second value different than the first value;

responsive to decreasing the set delay time from the second delay time, determine a third delay time as a value of the set delay time at which the value of the reception data is stabilized to the first value;

determining an optimum value of the set delay time based on the first delay time and the third delay time; and

delaying, by the optimum value, one of (i) the reception data signal and (ii) the reception clock signal with respect to the other of (i) and (ii),

wherein, when the latch circuit latches the first value while the set delay time is the initial value, the latch circuit uses one of the inverted reception data signal and the inverted reception clock signal for determining the first delay time, determining the second delay time, and determining the third delay time.