Host managed solid state drivecaching using dynamic write acceleration

1. A system comprising:

a non-volatile memory (NVM) communicatively coupled to a host computer apparatus, the NVM including a set of multi-level NVM cells organized into a dynamic single level cell buffer region corresponding to a fast NVM region, a static single level cell buffer region, and a dynamic multi-level NVM media region, and a chip controller apparatus that includes a substrate and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:

write a block of data addressed within the fast NVM region into the dynamic single cell buffer region under the control of the host computer;

write a block of data addressed outside the fast NVM region into the static single level cell buffer region; and

automatically write the contents of the static single level cell buffer region into the dynamic multi-level NVM media region;

wherein the fast NVM region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region addressable under the control of the host computer, and

wherein the multi-level NVM cells are dynamically convertible into and from single NVM cells.

2. The system of claim 1 , wherein the host computer apparatus is to receive write requests for blocks of data and determine whether the blocks of data are to be stored within the fast NVM region.

3. The system of claim 1 , wherein the fast NVM region comprises single level NVM cells.

4. The system of claim 3 , wherein the unused multi-level NVM cells are to be converted to single level NVM cells based upon the number of times data has been written into the cells.

5. The system of claim 4 , wherein the fast NVM region is to utilize an oldest cache block removal policy.

6. The system of claim 4 , wherein the fast NVM region is accessed using vendor specific commands.

7. The system of claim 1 , wherein the set of multi-level NVM cells includes a quad level cell architecture.

8. The system of claim 1 , wherein the set of multi-level NVM cells includes a tri-level cell architecture.

9. The system of claim 1 , wherein the dynamic single level cell buffer region of the fast NVM region is to be disabled and all write operations are to be into the static single level cell buffer region when the number of unused cells within the dynamic multi-level NVM media region is below a predetermined threshold.

10. An apparatus comprising:

a substrate; and

logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:

write a block of data addressed within a fast NVM region into a dynamic single cell buffer region under the control of a host computer;

write a block of data addressed outside the fast NVM region into a static single level cell buffer region; and

automatically write the contents of the static single level cell buffer region into a dynamic multi-level NVM media region;

wherein the fast NVM region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region addressable under the control of the host computer, and

wherein the multi-level NVM cells are dynamically convertible into and from single NVM cells.

11. The apparatus of claim 10 , wherein the fast NVM region comprises single level NVM cells.

12. The apparatus of claim 10 , wherein the logic is to further receive write requests for blocks of data and determine whether the blocks of data are to be stored within the fast NVM region.

13. The apparatus of claim 11 , wherein the unused multi-level NVM cells are to be converted to single level NVM cells based upon the number of times data has been written into the cells.

14. The apparatus of claim 13 , wherein the fast NVM region is accessed using vendor specific commands.

15. The apparatus of claim 13 , wherein the fast NVM region is to utilize a least frequently read cache block removal policy.

16. The apparatus of claim 10 , wherein the set of multi-level NVM cells is to include a quad level cell architecture.

17. The apparatus of claim 10 , wherein the set of multi-level NVM cells is to include a tri-level cell architecture.

18. The apparatus of claim 10 , wherein the dynamic single level cell buffer region of the fast NVM region is disabled and all write operations are into the static single level cell buffer region when the number of unused cells within the dynamic multi-level NVM media region is below a predetermined threshold.

19. A method comprising:

writing a block of data addressed within a fast NVM region into a set of multi-level NVM cells organized into a dynamic single level cell buffer region under the control of a host computer;

writing a block of data addressed outside the fast NVM region into the set of multi-level NVM cells organized into a static single level cell buffer region; and

automatically writing the contents of the static single level cell buffer region into a dynamic multi-level NVM media region;

wherein the fast NVM region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region addressable under the control of the host computer, and

wherein the multi-level NVM cells are dynamically convertible into and from single NVM cells.

20. The method of claim 19 , wherein the fast NVM region comprises single level NVM cells.

21. The method of claim 19 , wherein the fast NVM region is accessed using vendor specific commands.

22. The method of claim 19 , wherein the fast NVM region utilizes a least frequently read cache block removal policy.

23. The method of claim 19 , wherein the set of multi-level NVM cells includes a quad level cell architecture.

24. The method of claim 19 , wherein the set of multi-level NVM cells includes a tri-level cell architecture.