IP Library Granted Patent US 10,242,936
Granted Patent B2
US 10,242,936 · App. 15/680,802 · Granted Mar 26, 2019

Semiconductor device and method of fabricating the semiconductor device

Inventors: Junji Kotani (Atsugi, JP); Norikazu Nakamura (Sagamihara, JP)
Assignee: FUJITSU LIMITED
H01L23/49568H01L29/0649H01L29/2003H01L29/66462H01L29/7786H03F1/3247H03F3/195H03F3/245H01L29/0657H01L2023/4068
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Quick Facts
Patent No.
US 10,242,936
App. No.
15/680,802
Granted
Mar 26, 2019
Kind
B2
Abstract

A disclosed semiconductor device includes a buffer layer formed of a compound semiconductor on a substrate, a first semiconductor layer formed of a compound semiconductor on the buffer layer, a second semiconductor layer formed of a compound semiconductor on the first semiconductor layer, a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, and a heat dissipation part formed below the gate electrode. In the semiconductor device, all or part of the second semiconductor layer and the first semiconductor layer is present between the gate electrode and the heat dissipation part, the heat dissipation part includes a heat dissipation layer and a first intermediate layer formed between the heat dissipation layer and both of the buffer layer and first semiconductor layer, and the heat dissipation layer is formed of a material containing carbon.

Claims (59)

1. A method for fabricating a semiconductor device, the method comprising:

sequentially forming on a substrate, with one or more compound semiconductors, a buffer layer, a first semiconductor layer, and a second semiconductor layer;

forming a groove in a back surface of the substrate;

forming a first intermediate layer on inner surfaces of the groove;

forming a heat dissipation layer on the first intermediate layer on the inner surfaces of the groove to form a heat dissipation part including the first intermediate layer and the heat dissipation layer that are integrally disposed on the inner surfaces of the groove; and

forming a gate electrode, a source electrode, and a drain electrode on the second semiconductor layer, wherein

the groove is formed in the back surface of the substrate by removing the substrate, the buffer layer, and a portion of the first semiconductor layer in a region of the back surface below the gate electrode, so that a thickness of the rest of the first semiconductor layer where the portion of the first semiconductor layer is removed to form the groove reaches a predetermined thickness,

the heat dissipation part is disposed below the gate electrode and above the back surface of the substrate,

the heat dissipation layer is formed of a material containing carbon, and

the thickness of the rest of the first semiconductor layer between the gate electrode and the heat dissipation part is 50 nm or more and 500 nm or less.

2. The method as claimed in claim 1 , further comprising:

forming a second intermediate layer on the first intermediate layer after the first intermediate layer is formed on the inner surfaces of the groove, wherein

the heat dissipation layer is formed on the second intermediate layer, and

the second intermediate layer is formed of a material including both an element contained in the first intermediate layer and carbon.

3. The method as claimed in claim 1 , further comprising:

removing, after the heat dissipation part is formed on the first intermediate layer, a portion of the heat dissipation part formed on the back surface of the substrate.

4. A semiconductor device comprising:

a buffer layer formed of a compound semiconductor on a substrate;

a first semiconductor layer formed of a compound semiconductor on the buffer layer;

a second semiconductor layer formed of a compound semiconductor on the first semiconductor layer;

a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer; and

a heat dissipation part formed in a groove in a back surface of the substrate and disposed below the gate electrode and above the back surface of the substrate, wherein

the groove is formed in the back surface of the substrate by removing the substrate, the buffer layer, and a portion of the first semiconductor layer in a region of the back surface below the gate electrode, so that a thickness of the rest of the first semiconductor layer where the portion of the first semiconductor layer is removed to form the groove reaches a predetermined thickness,

the entire second semiconductor layer and the rest of the first semiconductor layer are present between the gate electrode and the heat dissipation part,

the heat dissipation part includes a heat dissipation layer, and a first intermediate layer which is formed between the heat dissipation layer and the buffer layer and between the heat dissipation layer and the first semiconductor layer,

the heat dissipation layer is formed of a material containing carbon, and

the thickness of the rest of the first semiconductor layer between the gate electrode and the heat dissipation part is 50 nm or more and 500 nm or less.

5. The semiconductor device as claimed in claim 4 , wherein

the first semiconductor layer is formed of a material containing GaN, and

the second semiconductor layer is formed of a material containing AlGaN or InAlN.

6. The semiconductor device as claimed in claim 4 , wherein

the heat dissipation part is further formed below a region between the gate electrode and the source electrode.

7. The semiconductor device as claimed in claim 4 , wherein

the heat dissipation layer is formed of a material containing any of diamond, carbon nanotube, graphene, and nanodiamond.

8. The semiconductor device as claimed in claim 4 , wherein

the first intermediate layer is formed of a material containing any of SiC, AlC, SiCN, and carbon nitride.

9. The semiconductor device as claimed in claim 4 , wherein

the first intermediate layer is formed of a material containing SiN or AlN.

10. The semiconductor device as claimed in claim 4 , wherein

the heat dissipation part is further formed on a back surface of the substrate.

11. The semiconductor device as claimed in claim 4 , wherein

each of the compound semiconductors is a nitride semiconductor.

12. The semiconductor device as claimed in claim 4 , wherein

the thickness of the first intermediate layer is 10 nm or less.

13. A power supply device comprising:

the semiconductor device as claimed in claim 4 .

14. An amplifier comprising:

the semiconductor device as claimed in claim 4 .

15. The semiconductor device as claimed in claim 4 , wherein

the heat dissipation part is further formed below a region between the gate electrode and the drain electrode.

16. The semiconductor device as claimed in claim 15 , wherein

the depth from a top surface of the second semiconductor layer to the heat dissipation part increases as a distance from the gate electrode increases.

17. The semiconductor device as claimed in claim 4 , wherein

the heat dissipation part includes a second intermediate layer formed between the first intermediate layer and the heat dissipation layer, and

the second intermediate layer is formed of a material including both an element contained in the first intermediate layer and carbon.

18. The semiconductor device as claimed in claim 17 , wherein

the second intermediate layer is formed of a material containing any of SiC, AlC, SiCN, and carbon nitride.

19. The semiconductor device as claimed in claim 17 , wherein

the thickness of the second intermediate layer is 10 nm or less.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2017
From: KOTANI, JUNJI; NAKAMURA, NORIKAZU
To: FUJITSU LIMITED
Reel/Frame 043607/0254 →
Priority Claims (1)
JP 2016-173414 · Sep 6, 2016 · national
Continuity (1)
Related Publication 20180068923A1 · Mar 8, 2018