Semiconductor devices with trench gate structures in a semiconductor body with hexagonal crystal lattice
A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.
1. A semiconductor device comprising:
a plurality of trench gate structures in a semiconductor body with hexagonal crystal lattice, wherein a mean surface plane of a first surface is tilted with respect to a <1-100>crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degrees to 12 degrees and trench sidewalls of the plurality of trench gate structures are aligned with the (11-20) crystal plane; and
a plurality of transistor mesas formed from portions of the semiconductor body between neighboring trench gate structures of the plurality of trench gate structures, wherein sidewalls of the plurality of transistor mesas deviate from a normal to the mean surface plane by not more than 5 degrees.
2. The semiconductor device of claim 1 , wherein the first surface is a serrated surface that comprises first surface sections formed by (1-100) crystal planes and second surface sections that are tilted with respect to the first sections and that connect the first surface sections with each other.
3. The semiconductor device of claim 1 , wherein the off-axis angle is in a range from 3 to 8 degrees or from −3 to −8 degrees.
4. The semiconductor device of claim 1 , wherein the plurality of trench gate structures are stripe-shaped with a longitudinal axis parallel to a projection of the <1-100> crystal direction on the mean surface plane.
5. The semiconductor device of claim 1 , wherein the semiconductor body comprises silicon carbide of the 4H polytype.
6. The semiconductor device of claim 1 , wherein the plurality of transistor mesas comprise body zones forming first pn junctions with a drift structure and second pn junctions with source zones, the source zones formed between the body zones and the first surface.
7. The semiconductor device of claim 1 , further comprising: diode regions forming third pn junctions with the drift structure and overlapping with neighboring trench gate structures of the plurality of trench gate structures in a vertical projection orthogonal to the mean surface plane.
8. The semiconductor device of claim 1 , further comprising mesa contact structures extending from the mean surface plane into the plurality of transistor mesas and directly adjoining the source zones and the body zones.
9. The semiconductor device of claim 8 , wherein a vertical extension of the mesa contact structures in the semiconductor body is equal to or greater than a vertical extension of the plurality of trench gate structures.
10. The semiconductor device of claim 7 , further comprising trench contact structures extending from the first surface through the plurality of trench gate structures and directly adjoining the diode regions.
11. The semiconductor device of claim 10 , wherein a vertical extension of the trench contact structures is equal to or greater than a vertical extension of the plurality of trench gate structures.
12. The semiconductor device of claim 10 , wherein each of the plurality of trench gate structures include first spacer portions and second spacer portions of a gate electrode on opposite sides of the respective trench contact structures.
13. The semiconductor device of claim 10 , further comprising mesa contact structures extending from the mean surface plane into the plurality of transistor mesas and directly adjoining the source zones and the body zones.
14. The semiconductor device of claim 1 , further comprising diode mesas comprising at least portions of diode regions that form third pn junctions with the drift structure and that directly adjoin two neighboring trench gate structures of the plurality of trench gate structures, respectively, wherein transistor and diode mesas alternate at least along a first horizontal direction parallel to a longitudinal axis of the plurality of trench gate structures.
15. The semiconductor device of claim 14 , wherein a distance between the first surface and the third pn junctions is greater than a vertical extension of the plurality of trench gate structures perpendicular to the first surface.
16. The semiconductor device of claim 14 , wherein the diode regions include shielding portions in a vertical projection of the plurality of trench gate structures.
17. The semiconductor device of claim 16 , wherein the shielding portions do not overlap with the plurality of transistor mesas.
18. The semiconductor device of claim 14 , wherein the transistor and diode mesas further alternate, separated by trench gate structures of the plurality of trench gate structures, along a second horizontal direction orthogonal to the first horizontal direction.
19. The semiconductor device of claim 1 , wherein the drift structure comprises a lightly doped drift zone and current spread zones between the drift zone and the body zones, and a mean net dopant concentration in the current spread zones is at least twice as high as a mean net dopant concentration in the drift zone.
20. The semiconductor device of claim 1 , wherein the sidewalls of the plurality of transistor mesas are aligned with the <1-100> crystal direction.
21. The semiconductor device of claim 1 , wherein the first surface is planar.
22. The semiconductor device of claim 1 , wherein the trench sidewalls of the plurality of trench gate structures are substantially perpendicular to the first surface.
23. A semiconductor device comprising:
a plurality of trench gate structures in a semiconductor body with hexagonal crystal lattice, wherein a mean surface plane of a first surface is tilted with respect to a <1-100> crystal direction by an off-axis angle and trench sidewalls of the plurality of trench gate structures are aligned with the (11-20) crystal plane; and
a plurality of transistor mesas formed from portions of the semiconductor body between neighboring trench gate structures of the plurality of trench gate structures, wherein sidewalls of the plurality of transistor mesas deviate from a normal to the mean surface plane by not more than 5 degrees.
24. A semiconductor device comprising:
a plurality of trench gate structures in a semiconductor body with hexagonal crystal lattice, wherein a mean surface plane of a first surface is tilted with respect to a <1-100> crystal direction by an off-axis angle; and
a plurality of transistor mesas formed from portions of the semiconductor body between neighboring trench gate structures of the plurality of trench gate structures, wherein sidewalls of the plurality of transistor mesas are aligned with the (11-20) crystal plane and deviate from a normal to the mean surface plane by not more than 5 degrees.