Sensor circuit
Provided is a sensor circuit that has little possibility of being accidentally put into a test mode in response to an external input of noise or the like. The sensor circuit includes a clock generation circuit configured to output a control signal that is used to control intermittent operation to a physical quantity detection unit, and to output a sampling signal in a sleep period, a potential detection circuit configured to detect a potential at an output terminal and to output a detection signal, and a clock control circuit configured to output a mode switching signal that is a command to switch the clock generation circuit to a test mode, when a given signal pattern is detected in data that is obtained by sampling the detection signal based on the sampling signal.
1. A sensor circuit configured to perform intermittent operation that includes an active period and a sleep period, comprising:
a physical quantity detection unit configured to output a physical quantity detection signal that has one of two different potential levels depending on an applied physical quantity;
an output driver configured to output a logic signal to an output terminal in response to the physical quantity detection signal;
a clock generation circuit configured to output a control signal that is used to control the intermittent operation to the physical quantity detection unit, and configured to output a sampling signal in the sleep period;
a potential detection circuit configured to detect a potential at the output terminal, and to output a detection signal; and
a clock control circuit configured to receive an input of the sampling signal and an input of the detection signal, and configured to output a mode switching signal to the clock generation circuit, the mode switching signal being a command to switch the clock generation circuit to a test mode when a given signal pattern is detected in data that is obtained by sampling the detection signal based on the sampling signal.
2. A sensor circuit according to claim 1 ;
wherein the physical quantity detection signal output from the physical quantity detection unit is further input to the clock control circuit, and
wherein the clock control circuit is configured to output the mode switching signal that is a command to switch to a normal mode, when the physical quantity detection signal changes in the test mode.
3. A sensor circuit according to claim 1 , further comprising a counter configured to start counting in response to a change of the detection signal, and configured to output a timeout signal to the clock control circuit when a timeout period is reached, and
wherein the clock control circuit is configured to mask the sampling signal by using the timeout signal.
4. A sensor circuit according to claim 1 , further comprising a dead time control circuit configured to output a dead time signal to the clock control circuit for a given period after transition to the sleep period, and
wherein the clock control circuit is configured to mask the sampling signal by using the dead time signal.
5. A sensor circuit according to claim 1 , further comprising a reset circuit configured to output a reset signal to the clock control circuit when detecting that the detection signal is narrow in width, and
wherein the clock control circuit is configured to mask the sampling signal by using the reset signal.