BURST-SIZED LINKED LIST ELEMENTS FOR A QUEUE

1 . A method, comprising:

receiving metadata describing a first buffer;

generating a descriptor based on the metadata; and

storing the descriptor in an element, wherein the element is configured to store a predetermined number of descriptors, and wherein the element comprises an amount of memory corresponding to a burst size of a component configured to read the metadata to control access to the first buffer.

2 . The method of claim 1 , further comprising, in response to the predetermined number of descriptors being stored in the element:

storing, in the element, a pointer to a next element, wherein the next element comprises an amount of memory corresponding to the burst size of the component.

3 . The method of claim 2 , wherein a memory capacity to store the predetermined number of descriptors combined with a memory capacity to store the pointer is substantially equal to the burst size.

4 . The method of claim 1 wherein the descriptor comprises a memory location of the buffer.

5 . The method of claim 1 , wherein the descriptor comprises a size of the buffer.

6 . The method of claim 1 , further comprising:

receiving second metadata describing a second buffer;

generating a second descriptor based on the second metadata; and

storing the second descriptor in the element.

7 . The method of claim 6 , wherein a size of the first buffer is not equal to a size of the second buffer.

8 . The method of claim 1 , further comprising:

determining the burst size of the component; and

selecting the predetermined number of descriptors based on the determined burst size.

9 . The method of claim 8 , further comprising:

determining that a burst size of the component has changed to a second burst size; and

selecting a new predetermined number of descriptors based on the second burst size.

10 . Input circuitry configured to construct a queue comprising a plurality of elements, comprising:

element construction circuitry configured to:

receive metadata describing a first buffer;

generate a descriptor based on the metadata; and

store the descriptor in an element, wherein the element is configured to store a predetermined number of descriptors, and wherein the element comprises an amount of memory corresponding to a burst size of a component configured to read the metadata to control access to the first buffer.

11 . The input circuitry of claim 10 , wherein the element construction circuitry is further configured to:

determine that the predetermined number of descriptors has been stored in the element; and

store, in the element, a pointer to a next element, wherein the next element comprises an amount of memory corresponding to the burst size of the component.

12 . The input circuitry of claim 11 , wherein a memory capacity to store the predetermined number of descriptors combined with a memory capacity to store the pointer is substantially equal to the burst size.

13 . The input circuitry of claim 10 , wherein the descriptor comprises a memory location of the buffer.

14 . The input circuitry of claim 10 , wherein the descriptor comprises a size of the buffer.

15 . The input circuitry of claim 10 , wherein the element construction circuitry is further configured to:

receive second metadata describing a second buffer;

generate a second descriptor based on the second metadata; and

store the second descriptor in the element.

16 . The input circuitry of claim 15 , wherein a size of the first buffer is not equal to a size of the second buffer.

17 . The input circuitry of claim 10 , wherein the element construction circuitry is further configured to:

determine the burst size of the component; and

select the predetermined number of descriptors based on the determined burst size.

18 . The input circuitry of claim 17 , wherein the element construction circuitry is further configured to:

determine that a burst size of the component has changed to a second burst size; and

select a new predetermined number of descriptors based on the second burst size.

19 . A buffering system, comprising:

input circuitry configured to:

receive metadata describing a buffer stored in a first memory;

generate a descriptor based on the metadata; and

store the descriptor in an element in a queue stored in a second memory,

wherein the element is configured to store a predetermined number of descriptors, and wherein the element comprises an amount of memory corresponding to a burst size of a component configured to read the metadata to control access to the buffer; and

output circuitry configured to:

read a pointer to a next element in an element stored in a third memory;

transfer the next element in the queue into a third memory in a single burst;

until all descriptors have been read:

read a next descriptor in the next element; and

retrieve data from the first memory based on the descriptor; and

when all descriptors in the next element have been read, read a pointer in the next element that points to a subsequent next element in the queue.

20 . The buffering system of claim 19 , wherein the first memory comprises dynamic random access memory (DRAM).

21 . The buffering system of claim 19 , wherein the second memory comprises dynamic random access memory (DRAM).

22 . The buffering system of claim 19 , wherein the third memory comprises static random access memory (SRAM).