Superconducting digital phase rotator
An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.
1. A phase rotator circuit, comprising:
at least one stage comprising:
a set of inputs comprising an increment signal, a decrement signal, and one of an input interstage signal and a master clock;
a first clocked inverter, receiving the decrement signal and the one of the input interstage signal and the master clock as a clock, and producing a first inverter output;
a second clocked inverter, receiving the increment signal and the first inverted output as a clock, and producing a second inverter output;
a first clocked latch, receiving the increment signal and the first inverted output as a clock, and producing a latch output;
a T flip-flop receiving the second inverter output, and producing an inverted flip-flop output dependent on the second inverter output; and
a confluence buffer or multiplexer, receiving the latch output and the inverted flip-flop output, merging the inverted flip-flop output with the latch output and producing a buffer output latched in dependence on the master clock.
2. The phase rotator circuit according to claim 1 , further comprising a second clocked latch, receiving the buffer output and the master clock, and producing an output interstage signal.
3. The phase rotator circuit according to claim 2 , wherein the master clock has a clock rate of at least 32 GHz.
4. The phase rotator circuit according to claim 2 , further comprising a single flux quantum output amplifier configured to amplify the output interstage signal.
5. The phase rotator circuit according to claim 2 , wherein a respective stage receives a preceding stage output interstage signal from a respective preceding stage, and conveys the output interstage signal to a respective succeeding stage.
6. The phase rotator circuit according to claim 2 , further comprising a decimator configured to receive the output interstage signal and produce a decimated signal.
7. The phase rotator circuit according to claim 2 , further comprising a set of flip-flops driven by the output interstage signal, configured to produce quadrature outputs of a 4-phase clock.
8. The phase rotator circuit according to claim 1 , having a plurality of stages and receiving a plurality of increment signals and a plurality of decrement signals, wherein the plurality of increment signals and the plurality of decrement signals having binary weighting.
9. The phase rotator circuit according to claim 1 , having a plurality of stages and receiving a plurality of increment signals and a plurality of decrement signals, wherein the plurality of increment signals and the plurality of decrement signals having uniform weighting.
10. The phase rotator circuit according to claim 1 , having a plurality of stages, and having a serial divider circuit to produce a signal having 16 different phase states.
11. The phase rotator circuit according to claim 1 , comprising at least one Josephson junction.
12. The phase rotator circuit according to claim 1 , implemented with single flux quantum logic.
13. The phase rotator circuit according to claim 1 , implemented with superconducting digital logic.
14. The phase rotator according to claim 1 , wherein the buffer output comprises single flux quantum pulses.
15. The phase rotator circuit according to claim 1 , wherein the input interstage signal has a clock rate of at least 1 GHz.
16. The phase rotator circuit according to claim 1 , implemented in an integrated circuit.
17. The phase rotator circuit according to claim 1 , wherein the confluence buffer or multiplexer comprises a confluence buffer.
18. A digital phase rotation method, comprising:
providing at least one stage comprising:
a set of inputs comprising an increment signal, a decrement signal, and one of an input interstage signal and a master clock;
a first clocked inverter, receiving the decrement signal and the one of the input interstage signal and the master clock as a clock, and producing a first inverter output;
a second clocked inverter, receiving the increment signal and the first inverted output as a clock, and producing a second inverter output;
a first clocked latch, receiving the increment signal and the first inverted output as a clock, and producing a latch output;
a T flip-flop receiving the second inverter output, and producing an inverted flip-flop output;
a confluence buffer or multiplexer, receiving the latch output and the inverted flip-flop output and producing a buffer output; and
a second clocked latch, receiving the buffer output and the master clock, and producing an output interstage signal;
altering a state of the T flip-flop based on the second inverter output;
merging the inverted flip-flop output with the latch output to produce the buffer output; and
latching the buffer output dependent on the master clock.
19. A phase rotator circuit having a plurality of stages, each stage comprising:
a set of inputs comprising an increment signal, a decrement signal, and one of an input interstage signal;
a first inverter, receiving the decrement signal and being clocked based on the input interstage signal, and producing a first inverter output;
a second inverter, receiving the increment signal and being clocked based on the first inverted output, and producing a second inverter output;
a first clocked latch, receiving the increment signal and being clocked based on the first inverted output, and producing a latch output;
a T flip-flop receiving the second inverter output and having a state based on the second inverter output, producing an inverted flip-flop output;
a confluence buffer or multiplexer, receiving the latch output and the inverted flip-flop output, merging the inverted flip-flop output with the latch output, and producing a buffer output; and
a second clocked latch, receiving the buffer output and being clocked based on a master clock, and producing an output interstage signal.
20. The phase rotator circuit according to claim 19 , wherein a respective stage of the plurality of stages receives a preceding stage output interstage signal from a respective preceding stage, and conveys the output interstage signal to a respective succeeding stage.