Memory system that differentiates voltages applied to word lines
A memory system includes a semiconductor memory chip including a substrate, an array of memory cells in arranged each of a plurality of levels in a thickness direction of the substrate, and a plurality of word lines arranged in the thickness direction, each of the word lines being connected to memory cells in one of the levels, and a controller. The controller is configured to determine an offset value with respect to each of a plurality of word line groups that are organized from the plurality of word lines along the thickness direction, and, with respect to each of the word line groups, set a voltage to be applied to the word line group during at least one of write, read, and erase operations, based on a base parameter value and the offset value corresponding to the word line group.
1. A memory system comprising:
a semiconductor memory chip including a substrate and word lines stacked in a thickness direction above the substrate, each of the word lines connecting a plurality of memory cells, the word lines including a first word line connecting first memory cells and a second word line above the first word line connecting second memory cells that are above the first memory cells, wherein a size of each of the first memory cells is different from a size of each of the second memory cells; and
a controller configured to:
determine an offset value with respect to each of a plurality of word line groups, each of the word line groups including a plurality of the word lines, and
with respect to each of the word line groups, set a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the word line group and a base parameter value, wherein
during the write operation, the semiconductor memory chip applies as the voltage a plurality of write voltages, one of the write voltages having a voltage level that is incremented by a step voltage from a bias voltage and others of the write voltages having a voltage level that is incremented by the step voltage from another write voltage, and
the base parameter value corresponds to a base value of the step voltage, and the offset value corresponds to an offset value of the step voltage.
2. The memory system according to claim 1 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is lower than the voltage set for a word line in the first word line group.
3. The memory system according to claim 2 , wherein
the plurality of word line groups further includes a third word line group that is positioned closer to the substrate than the second word line group is, and
the voltage set for a word line in the third word line group is lower than the voltage set for the word line in the second word line group.
4. The memory system according to claim 1 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is higher than the voltage set for a word line in the first word line group.
5. The memory system according to claim 1 , wherein
the semiconductor memory chip includes a plurality of voltage applying circuits each of which applies the voltage set for a word line in one of the word line groups to said one of the word line groups.
6. The memory system according to claim 1 , wherein
the controller is further configured to determine a deterioration degree with respect to each of the word line groups, and
each of the offset values for the plurality of word line groups varies depending on the deterioration degree.
7. The memory system according to claim 1 , wherein the controller is further configured to:
determine an offset value with respect to each of a plurality of memory cell groups, each of the memory cell groups including memory cells that are connected to one of the word line groups and are formed in the thickness direction along one of a plurality of pillars that extend in the thickness direction and are arranged along a surface direction of the substrate, and
with respect to each of the memory cell groups, set a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the memory cell group and the base parameter value.
8. A memory system comprising:
a semiconductor memory chip including a substrate and word lines stacked in a thickness direction above the substrate, each of the word lines connecting a plurality of memory cells, the word lines including a first word line connecting first memory cells and a second word line above the first word line connecting second memory cells that are above the first memory cells, wherein a size of each of the first memory cells is different from a size of each of the second memory cells; and
a controller configured to:
determine an offset value with respect to each of a plurality of word line groups, each of the word line groups including a plurality of the word lines, and
with respect to each of the word line groups, set a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the word line group and a base parameter value, wherein
during the write operation, the semiconductor memory chip applies as the voltage a plurality of write voltages, one of the write voltages having a voltage level that is incremented by a step voltage from a bias voltage and others of the write voltages having a voltage level that is incremented by the step voltage from another write voltage, and
the base parameter value corresponds to a base value of the bias voltage, and the offset value corresponds to an offset value of the bias voltage.
9. The memory system according to claim 8 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is lower than the voltage set for a word line in the first word line group.
10. The memory system according to claim 9 , wherein
the plurality of word line groups further includes a third word line group that is positioned closer to the substrate than the second word line group is, and
the voltage set for a word line in the third word line group is lower than the voltage set for the word line in the second word line group.
11. The memory system according to claim 8 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is higher than the voltage set for a word line in the first word line group.
12. The memory system according to claim 8 , wherein
the semiconductor memory chip includes a plurality of voltage applying circuits each of which applies the voltage set for a word line in one of the word line groups to said one of the word line groups.
13. The memory system according to claim 8 , wherein
the controller is further configured to determine a deterioration degree with respect to each of the word line groups, and
each of the offset values for the plurality of word line groups varies depending on the deterioration degree.
14. The memory system according to claim 8 , wherein the controller is further configured to:
determine an offset value with respect to each of a plurality of memory cell groups, each of the memory cell groups including memory cells that are connected to one of the word line groups and are formed in the thickness direction along one of a plurality of pillars that extend in the thickness direction and are arranged along a surface direction of the substrate, and
with respect to each of the memory cell groups, set a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the memory cell group and the base parameter value.
15. A method for controlling a memory system including a semiconductor memory chip that includes a substrate and word lines stacked in a thickness direction above the substrate, each of the word lines connecting a plurality of memory cells, the word lines including a first word line connecting first memory cells and a second word line above the first word line connecting second memory cells that are above the first memory cells, wherein a size of each of the first memory cells is different from a size of each of the second memory cells, the method comprising:
determining an offset value with respect to each of a plurality of word line groups, each of the word line groups including a plurality of the word lines;
with respect to each of the word line groups, setting a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the word line group and a base parameter value; and
during the write operation, applying as the voltage a plurality of write voltages, one of the write voltages having a voltage level that is incremented by a step voltage from a bias voltage and others of the write voltages having a voltage level that is incremented by the step voltage from another write voltage, wherein
the base parameter value corresponds to a base value of the bias voltage, and the offset value corresponds to an offset value of the bias voltage.
16. The method according to claim 15 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is lower than the voltage set for a word line in the first word line group.
17. The method according to claim 16 , wherein
the plurality of word line groups further includes a third word line group that is positioned closer to the substrate than the second word line group is, and
the voltage set for a word line in the third word line group is lower than the voltage set for the word line in the second word line group.
18. The method according to claim 15 , wherein
the plurality of word line groups includes a first word line group and a second word line group that is positioned closer to the substrate than the first word line group is, and
the voltage set for a word line in the second word line group is higher than the voltage set for a word line in the first word line group.
19. The method according to claim 15 , further comprising:
determining a deterioration degree with respect to each of the word line groups, wherein each of the offset values for the plurality of word line groups varies depending on the deterioration degree.
20. The method according to claim 15 , further comprising:
determining an offset value with respect to each of a plurality of memory cell groups, each of the memory cell groups including memory cells that are connected to one of the word line groups and are formed in the thickness direction along one of a plurality of pillars that extend in the thickness direction and are arranged along a surface direction of the substrate; and
with respect to each of the memory cell groups, setting a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the memory cell group and the base parameter value.