IP Library Granted Patent US 10,579,421
Granted Patent B2
US 10,579,421 · App. 15/687,172 · Granted Mar 3, 2020

Dynamic scheduling of virtual processors in a distributed system

Inventors: Isaac R. Nassi (Los Gatos, CA); Mark Hill (Los Altos, CA); I-Chun Fang (San Jose, CA); Kleoni Ioannidou (Sunnyvale, CA)
Assignee: TidalScale, Inc.
G06F9/4875G06F9/3009G06F9/30123G06F9/3855G06F9/44G06F9/45558G06F9/4856G06F9/4881G06F9/5055G06F9/5077G06F9/546H04L67/10G06F2009/4557
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Quick Facts
Patent No.
US 10,579,421
App. No.
15/687,172
Granted
Mar 3, 2020
Kind
B2
Abstract

Dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. In response to receiving an indication of an event occurring, a search is performed for a queue in a set of queues on which to place a virtual processor that had been waiting on the event. Queues in the set of queues correspond to hyperthreads in a physical node in the plurality of physical nodes. The queues in the set of queues are visited according to a predetermined traversal order.

Claims (21)

1. A computer system, comprising:

a plurality of physical nodes, wherein each node includes a plurality of processors;

wherein each of the processors includes a plurality of hyperthreads; and

wherein in response to receiving an indication of a resource that a stalled virtual processor had been waiting on becoming available, resuming of the stalled virtual processor is scheduled at least in part by placing a representation of the stalled virtual processor in a work queue of stalled virtual processors to be resumed by a hyperthread, wherein the scheduling comprises:

traversing, according to a predetermined traversal order, a set of work queues corresponding to a respective set of hyperthreads on a physical node in the plurality of physical nodes, wherein a given work queue is accessible by a corresponding hyperthread; and

in response to determining that all work queues in the set of work queues corresponding to the respective set of hyperthreads on the physical node are full, evicting a previously queued virtual processor from the set of work queues corresponding to the respective set of hyperthreads on the physical node, wherein the resource is on the physical node, wherein evicting the previously queued virtual processor is based at least in part on a comparison of a performance of the stalled virtual processor on the physical node relative to performance of previously queued virtual processors on the physical node, and wherein the evicted virtual processor is placed in a global work queue accessible to hyperthreads across the plurality of physical nodes.

2. The computer system of claim 1 , wherein the evicted virtual processor comprises a poorest performing virtual processor in the set of work queues.

3. The computer system of claim 1 , wherein the evicted virtual processor is evicted based at least in part on a measure of efficiency associated with a guest thread that had been running in the evicted virtual processor.

4. The computer system of claim 1 , wherein the stalled virtual processor is placed on a queue from which the evicted virtual processor was evicted.

5. The computer system of claim 1 , wherein the predetermined traversal order mimics a tree walk.

6. The computer system of claim 1 , wherein the traversal begins from a queue corresponding to a hyperthread on which the stalled virtual processor last ran.

7. A method, comprising:

receiving an indication of a resource that a stalled virtual processor had been waiting on becoming available; and

in response to receiving the indication of the resource that the stalled virtual processor had been waiting on becoming available, scheduling resuming of the stalled virtual processor at least in part by placing a representation of the stalled virtual processor in a work queue of stalled virtual processors to be resumed by a hyperthread, wherein the scheduling comprises:

traversing, according to a predetermined traversal order, a set of work queues corresponding to a respective set of hyperthreads on a physical node in a plurality of physical nodes, wherein a given work queue is accessible by a corresponding hyperthread; and

in response to determining that all work queues in the set of work queues corresponding to the respective set of hyperthreads on the physical node are full, evicting a previously queued virtual processor from the set of work queues corresponding to the respective set of hyperthreads on the physical node, wherein the resource is on the physical node, wherein evicting the previously queued virtual processor is based at least in part on a comparison of a performance of the stalled virtual processor on the physical node relative to performance of previously queued virtual processors on the physical node, and wherein the evicted virtual processor is placed in a global work queue accessible to hyperthreads across the plurality of physical nodes.

8. The method of claim 7 , wherein the evicted virtual processor comprises a poorest performing virtual processor in the set of work queues.

9. The method of claim 7 , wherein the evicted virtual processor is evicted based at least in part on a measure of efficiency associated with a guest thread that had been running in the evicted virtual processor.

10. The method of claim 7 , wherein the stalled virtual processor is placed on a queue from which the evicted virtual processor was evicted.

11. The method of claim 7 , wherein the predetermined traversal order mimics a tree walk.

12. The method of claim 7 , wherein the traversal begins from a queue corresponding to a hyperthread on which the stalled virtual processor last ran.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2023
From: TIDALSCALE, INC.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 062282/0452 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 060724/0458 Recorded Dec 30, 2022
From: COMERICA BANK
To: TIDALSCALE, INC.
Reel/Frame 062252/0199 →
RELEASE OF SECURITY INTEREST Recorded Dec 15, 2022
From: COMERICA BANK
To: TIDALSCALE, INC.
Reel/Frame 062108/0963 →
SECURITY INTEREST Recorded Aug 4, 2022
From: TIDALSCALE, INC.
To: COMERICA BANK
Reel/Frame 060724/0458 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2017
From: NASSI, ISAAC R.; HILL, MARK; FANG, I-CHUN; IOANNIDOU, KLEONI
To: TIDALSCALE, INC.
Reel/Frame 043823/0928 →
Continuity (6)
Provisional Application 62457609 · Feb 10, 2017
Provisional Application 62380896 · Aug 29, 2016
Provisional Application 62468856 · Mar 8, 2017
Provisional Application 62525544 · Jun 27, 2017
Provisional Application 62525552 · Jun 27, 2017
Related Publication 20180060121A1 · Mar 1, 2018