Repeatable backchannel link adaptation for high speed serial interfaces
A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.
1. A receiver, comprising:
a first signal processing chain including a first gain circuit, a first equalization circuit of a first type, and a second equalization circuit of a second type, the first equalization circuit configured to receive a data bitstream received by the receiver to generate a selectable first compensation value, the first gain circuit directly connected to the first equalization circuit and configured to receive the selectable first compensation value of the first equalization circuit to generate a selectable first gain value, and the second equalization circuit directly connected to the first gain circuit and configured to receive the selectable first gain value of the first gain circuit to generate a selectable second compensation value; and
a second signal processing chain including a second gain circuit, a third equalization circuit of the first type, a fourth equalization circuit of the second type, and a slicer, the third equalization circuit configured to receive the data bitstream to generate a selectable third compensation value, the second gain circuit directly connected to the third equalization circuit and configured to receive the selectable third compensation value of the third equalization circuit to generate a selectable second gain value, the fourth equalization circuit directly connected to the second gain circuit and configured to receive the selectable second gain value of the second gain circuit to generate a selectable fourth compensation value, and the slicer configured to receive the selectable fourth compensation value of the fourth equalization circuit to determine a characteristic based on the selectable fourth compensation value, wherein the first equalization circuit is separate from the third equalization circuit and the second equalization circuit is separate from the fourth equalization circuit.
2. The receiver of claim 1 , wherein the characteristic comprises an eye height.
3. The receiver of claim 2 , wherein the slicer is further configured to receive a voltage offset or a vertical offset to determine the eye height.
4. The receiver of claim 2 , wherein the characteristic further comprises an eye width.
5. The receiver of claim 4 , wherein the slicer is further configured to receive a phase rotator or a timing offset to determine the eye width.
6. The receiver of claim 1 , wherein the characteristic comprises a bit error rate.
7. The receiver of claim 1 , further comprising:
a multiplexor configured to receive the data bitstream and to selectably provide the data bitstream to one of the first signal processing chain and the second signal processing chain.
8. The receiver of claim 1 , wherein the first type comprises a continuous time linear equalizer and the second type comprises a decision feedback equalizer.
9. A method, comprising:
receiving, at a first signal processing chain of a receiver, a data bitstream received by the receiver;
generating, by a first equalization circuit of the first signal processing chain, a selectable first compensation value, wherein the first equalization circuit is of a first type;
obtaining, by the first equalization circuit, the selectable first compensation value based on the data bitstream;
generating, by a first gain circuit of the first signal processing chain, a selectable first gain value, wherein the first gain circuit is directly connected to the first equalization circuit:
obtaining, by the first gain circuit, the selectable first gain value based upon the selectable first compensation value of the first equalization circuit;
generating, by a second equalization circuit of the first signal processing chain, a selectable second compensation value, wherein the second equalization circuit is of a second type, wherein the second equalization circuit is directly connected to the first gain circuit;
obtaining, by the second equalization circuit, the selectable second compensation value based on the selectable first gain value of the first gain circuit;
receiving, at a second signal processing chain of the receiver, the data bitstream;
generating, by a third equalization circuit of the second signal processing chain, a selectable third compensation value, wherein the third equalization circuit is of the first type, and wherein the third equalization circuit is separate from the first equalization circuit;
obtaining, by the third equalization circuit, the selectable third compensation value based on the data bitstream;
generating, by a second gain circuit of the second signal processing chain, a selectable second gain value, wherein the second gain circuit is directly connected to the third equalization circuit;
obtaining, by the second gain circuit, the selectable second gain value based upon the selectable third compensation value of the third equalization circuit;
generating, by a fourth equalization circuit of the second signal processing chain, a selectable fourth compensation value, wherein the fourth equalization circuit is of the second type, wherein the fourth equalization circuit is directly connected to the second gain circuit, and wherein the fourth equalization circuit is separate from the second equalization circuit;
obtaining, by the fourth equalization circuit, the selectable fourth compensation value based on the selectable second gain value of the second gain circuit; and
determining, by a slicer of the second signal processing chain, a characteristic based on the selectable fourth compensation value.
10. The method of claim 9 , wherein the characteristic comprises an eye height.
11. The method of claim 10 , wherein in determining the characteristic, the method further comprises:
receiving, by the slicer, a voltage offset or a vertical offset to determine the eye height.
12. The method of claim 10 , wherein the characteristic further comprises an eye width.
13. The method of claim 12 , wherein in determining the characteristic, the method further comprises:
receiving, by the slicer, a phase rotator or a timing offset to determine the eye width.
14. The method of claim 9 , wherein the characteristic comprises a bit error rate.
15. The method of claim 9 , further comprising:
receiving, by a multiplexor of the receiver, the data bitstream; and
selectably providing, by the multiplexor, the data bitstream to one of the first signal processing chain and the second signal processing chain.
16. The method of claim 9 , wherein the first type comprises a continuous time linear equalizer and the second type comprises a decision feedback equalizer.
17. A receiver, comprising:
a first signal processing chain including a first continuous time linear equalization circuit, a first gain circuit, and a first decision feedback equalization circuit, the first continuous time linear equalization circuit configured to receive a data bitstream received by the receiver to generate a selectable first equalization value, the first gain circuit directly connected to the first continuous time linear equalization circuit and configured to receive the selectable first equalization value of the first continuous time linear equalization circuit to generate a selectable first gain value, and the first decision feedback equalization circuit directly connected to the first gain circuit and configured to receive the selectable first gain value of the first gain circuit to generate a selectable second equalization value;
a second signal processing chain including a second continuous time linear equalization circuit, a second gain circuit, a second decision feedback equalization circuit, and a slicer, the second continuous time linear equalization circuit configured to receive the data bitstream to generate a selectable third equalization value, the second gain circuit directly connected to the second continuous time linear equalization circuit and configured to receive the selectable third equalization value of the second continuous time linear equalization circuit to generate a selectable second gain value, the second decision feedback equalization circuit directly connected to the second gain circuit and configured to receive the selectable second gain value of the second gain circuit to generate a selectable fourth equalization value, and the slicer configured to determine an eye height and an eye width based on the selectable fourth equalization value; and
control logic configured to record the selectable third equalization value and the selectable fourth equalization value associated with the determined eye height and eye width;
wherein the first and second continuous time linear equalization circuits are separate continuous time linear equalization circuits, and wherein the first and second decision feedback equalization circuits are separate decision feedback equalization circuits.
18. The receiver of claim 17 , wherein the slicer is further configured to receive a voltage offset or a vertical offset to determine the eye height.
19. The receiver of claim 17 , wherein the slicer is further configured to receive a phase rotator or a timing offset to determine the eye width.
20. The receiver of claim 17 , further comprising:
a multiplexor configured to selectably provide the data bitstream to one of the first signal processing chain and the second signal processing chain.