Enhanced digital diagnostics for optical PAM apparatus
A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.
1. A method comprising:
collecting data in a debugging memory of an optical transceiver of a module;
communicating the data from the debugging memory to an engine of a master logic system;
the engine of the master logic system processing the data to produce parametric information relevant for diagnostic purposes; and
housing the parametric information in a new register of the master logic system.
2. The method of claim 1 wherein:
the data comprises equalizer output data; and
the parametric information comprises an estimated link slicer signal-to-noise ratio (SNR) produced by,
slicing the equalizer output data using converged PAM levels and slicer thresholds internally driven by a DSP control loop,
labeling a discrepancy between the equalizer output and an expected PAM level as an error signal, and
calculating the estimated link slicer SNR as a ratio between an average level power and an error signal mean square.
3. The method of claim 1 wherein:
the data comprises equalizer output data; and
the parametric information comprises an estimated channel pulse response produced by a least-square channel estimation employing a symbol provided by a symbol decision within a digital signal processor (DSP) or a Pseudo-Random Binary Sequence (PRBS) generator.
4. The method of claim 3 further comprising determining a linear residual linear Inter Symbol Interference (ISI) component from the estimated channel pulse response.
5. The method of claim 4 further comprising determining a non-linear ISI component by subtracting the residual linear ISI component from a signal.
6. The method of claim 4 further comprising matching the residual component to a form of non-linear ISI according to a nonlinearity model.
7. The method of claim 4 further comprising filling a look-up-table (LUT) with an average of the residual component for each data pattern.
8. The method of claim 4 further comprising:
extracting the linear ISI component and a non-linear ISI component from a signal to leave a remaining signal; and
performing noise characterization on the remaining signal by estimating a noise variance and correlation per data pattern.
9. The method of claim 1 further comprising communicating the parametric information across an interface to a host for further diagnostic processing.
10. The method of claim 1 wherein the parametric information comprises a Feed Forward Equalization (FFE) output, the method further comprising:
the engine of the master logic system processing the parametric information with additional parametric information comprising slicer information to produce second diagnostic information comprising a Bit Error Rate (BER) of a Forward Error Correction (FEC) function.
11. The method of claim 1 wherein the data comprises an Analog-to-Digital Conversion (ADC) output.
12. The method of claim 1 wherein the parametric information comprises an eye diagram.
13. The method of claim 1 wherein the parametric information comprises an eye histogram collected by populating post-equalization sample hits until a single bin saturates.
14. The method of claim 1 wherein the parametric information comprises a first error signal, the method further comprising:
the engine of the master logic system processing the parametric information with additional parametric information comprising a second error signal to produce an estimated Mean Square Error (MSE) based upon the first error signal and the second error signal.
15. The method of claim 1 wherein the parametric information comprises a frame error.
16. The method of claim 15 wherein the frame error comprises a module frame error count or errored seconds.
17. The method of claim 1 wherein the data utilizes forward error correction (FEC), the method further comprising:
the engine of the master logic system processing the parametric information with additional parametric information selected from a FEC bit error rate, a FEC mode, and a FEC enable/disable.
18. The method of claim 17 wherein the additional parametric information comprises a bit error rate (BER).
19. The method of claim 18 wherein the BER comprises a per-level BER, the method further comprising storing the BER in another new register of the master logic system.
20. The method of claim 19 wherein above a FEC limit, the BER is estimated based on Signal-to-Noise Ratio (SNR).