IP Library Granted Patent US 10,256,726
Granted Patent B2
US 10,256,726 · App. 15/688,542 · Granted Apr 9, 2019

Voltage conversion apparatus including output unit, comparator, delay circuit, and control circuit

Inventor: Tatsuhiko Maruyama (Kawasaki Kanagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
H02M3/158H02M1/08H02M1/14H02M3/156H02M2001/0025
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Quick Facts
Patent No.
US 10,256,726
App. No.
15/688,542
Granted
Apr 9, 2019
Kind
B2
Abstract

A voltage conversion apparatus includes an output unit connected to an input voltage to output an output voltage according to a control signal. A comparator compares a reference voltage to a feedback voltage corresponding to the output voltage and outputs a comparison signal. A delay circuit outputs a delayed signal obtained by delaying either a rising timing or a falling timing of the comparison signal. The delay circuit varies a delay time of the delayed signal on basis of a modulating signal. A control circuit is configured to output the control signal to the output unit. The control signal is based on the delayed signal. The control circuit controls the output unit such that a frequency of the output voltage is tuned to a predetermined value set according to the modulating signal.

Claims (20)

1. A voltage conversion apparatus, comprising:

an output unit connected to an input voltage and configured to output an output voltage according to a control signal supplied to the output unit;

a comparator configured to compare a reference voltage to a feedback voltage corresponding to the output voltage and output a comparison signal corresponding to the comparison;

a delay circuit configured to output a delayed signal obtained by delaying either a rising timing or a falling timing of the comparison signal output from the comparator, the delay circuit varying a delay time of the delayed signal on basis of a modulating signal; and

a control circuit configured to output the control signal to the output unit, the control signal being based on the delayed signal, the control circuit controlling the output unit such that a frequency of the output voltage is tuned to a predetermined value set according to the modulating signal, wherein

the delay circuit comprises:

a pair of output transistors connected in series, gates of the output transistors being commonly connected to the comparator and receiving the comparison signal;

a constant current source connected to one end of the pair of output transistors, another end of the pair of output transistors being connected to a reference potential;

a capacitor connected between the reference potential and an output node of the pair of output transistors;

a second comparator having one input connected to the output node of the pair of transistors and the capacitor and a second input receiving a reference signal; and

an OR logical unit receiving as inputs a second comparison signal from the second comparator and the comparison signal from the first comparator.

2. The voltage conversion apparatus according to claim 1 , wherein the predetermined value is a frequency of the modulating signal.

3. The voltage conversion apparatus according to claim 1 , wherein the delay circuit changes the delay time on the basis of the modulating signal.

4. The voltage conversion apparatus according to claim 1 , wherein the delay circuit generates a modulation voltage that changes on the basis of the modulating signal, and changes the delay time on the basis of the modulation voltage.

5. The voltage conversion apparatus according to claim 1 , wherein the delay circuit changes a capacitance acting on the delay circuit on the basis of the modulating signal, and changes the delay time on the basis of the capacitance.

6. The voltage conversion apparatus according to claim 1 , further comprising:

a flip-flop circuit receiving the comparison signal at a reset terminal and the delayed signal at a set terminal, a Q terminal of the flip-flop circuit being connected to a switch.

7. The voltage conversion apparatus according to claim 1 , wherein the pair of output transistors comprises a p-channel transistor and an n-channel transistor and the output node is between the p-channel transistor and the n-channel transistor.

8. The voltage conversion apparatus according to claim 1 , further comprising:

a ripple rejection filter connected to an output node of the output unit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2025
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: INTERNATIONAL SEMICONDUCTOR GROUP
Reel/Frame 070785/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2024
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 068143/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: MARUYAMA, TATSUHIKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 044023/0392 →
Priority Claims (1)
JP 2017-037125 · Feb 28, 2017 · national
Continuity (1)
Related Publication 20180248483A1 · Aug 30, 2018