SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.
1 . A semiconductor memory device comprising:
a semiconductor substrate;
a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers;
a second insulating layer which covers the stepped structure;
a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer; and
a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.
2 . The semiconductor memory device according to claim 1 , wherein the second conductive layer is between the first and third conductive layers in the thickness direction of the semiconductor substrate.
3 . The semiconductor memory device according to claim 2 , further comprising;
a third contact interconnection which penetrates the second insulating layer and the third conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to another one of the conductive layer.
4 . The semiconductor memory device according to claim 3 , wherein the second contact interconnection is between the first and third contact interconnections.
5 . The semiconductor memory device according to claim 1 , wherein
the first contact interconnection also penetrates another one of the conductive layers above the first conductive layer in the thickness direction of the semiconductor substrate; and
the second contact interconnection also penetrates the first conductive layer in a thickness direction of the semiconductor substrate.
6 . The semiconductor memory device according to claim 1 , further comprising a first insulating film disposed on side surfaces of the first and second contact interconnections, wherein the first insulating film contacts portions of the plurality of conductive layers through which the first and second contact interconnections penetrate.
7 . The semiconductor memory device according to claim 1 , wherein the first and second contact interconnections each penetrate the same number of conductive layers.
8 . The semiconductor memory device according to claim 1 , wherein each of the first and second contact interconnections includes an enlarged diameter portion having an enlarged diameter compared to upper and lower portions thereof that are surrounded by the same conductive layer.
9 . The semiconductor memory device according to claim 1 , further comprising:
a third insulating layer which covers the second insulating layer, wherein
the second insulating layer is a silicon oxide layer, and the third insulating layer is a silicon nitride layer.
10 . A method of manufacturing a semiconductor memory device comprising:
forming a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of a semiconductor substrate, the conductive layers including first, second, and third conductive layers;
forming a second insulating layer which covers the stepped structure;
forming a first contact hole which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and reaches the second conductive layer, and a second contact hole which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and reaches the third conductive layer; and
depositing conductive material in the first and second contact holes to form first and second contact interconnections, respectively.
11 . The method of claim 10 , wherein the forming of the contact hole comprises:
performing etching on the stepped structure to penetrate an upper conductive layer formed above a target conductive layer in the plurality of conductive layers until the target conductive layer is exposed.
12 . The method of claim 11 , wherein the first and second contact holes penetrate the same number of conductive layers.
13 . The method of claim 11 , further comprising:
forming a third insulating layer which covers the second insulating layer, wherein
the second insulating layer is a silicon oxide layer, and the third insulating layer is a silicon nitride layer.
14 . The method of claim 13 , wherein forming the stepped structure includes:
forming a stacked body including the plurality of first insulating layers and first sacrificial insulating layers which are alternately stacked on the main surface of the semiconductor substrate;
forming the second insulating layer which covers the stacked body;
etching the stacked body to remove the plurality of first sacrificial insulating layers; and
depositing conductive material in spaces created by removing the plurality of first sacrificial insulating layers.
15 . The method of claim 14 , wherein:
a silicon oxide film is used for the second insulating layer and the plurality of first insulating layers; and
a silicon nitride film is used for the plurality of first sacrificial insulating layers.
16 . The method of claim 15 , wherein the forming of the contact hole comprises:
forming a first contact hole portion having a depth reaching the first conductive layer by anisotropic dry etching;
forming a second contact hole portion by etching the first conductive layer that is exposed by the first contact hole portion; and
forming a third contact hole portion by etching the first insulating layer that is exposed by the second contact hole portion by anisotropic dry etching.
17 . The method of claim 16 , wherein forming the first contact hole portion includes:
etching the second insulating layer by the anisotropic dry etching with the third insulating film serving as an etch stopper.
18 . The method of claim 10 , further comprising:
forming a first insulating film which covers side walls of the first and second contact holes; and
depositing the conductive material in the first and second contact holes having the first insulating film formed on side walls thereof.
19 . A method of manufacturing a semiconductor memory device, comprising:
forming a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of a semiconductor substrate, the conductive layers including first, second, third, and fourth conductive layers;
forming a second insulating layer which covers the stepped structure; and
forming a first contact hole which penetrates the second insulating layer and the first and second conductive layers in a thickness direction of the semiconductor substrate, and reaches the third conductive layer, and a second contact hole which penetrates the second insulating layer and the second and third conductive layers in the thickness direction of the semiconductor substrate, and reaches the fourth conductive layer,
wherein the third conductive layer is the conductive layer to which a first contact interconnection formed in the first contact hole is electrically connected, and the fourth conductive layer is the conductive layer to which a second contact interconnection formed in the second contact hole is electrically connected.
20 . The method of claim 19 , wherein when forming of the contact hole, the first and second contact holes penetrate the same number of the conductive layers.