IP Library Granted Patent US 10,211,739
Granted Patent B2
US 10,211,739 · App. 15/692,071 · Granted Feb 19, 2019

Methods and apparatus for an integrated circuit

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Quick Facts
Patent No.
US 10,211,739
App. No.
15/692,071
Granted
Feb 19, 2019
Kind
B2
Abstract

Various embodiments of the present technology may comprise methods and apparatus for an integrated circuit (IC). The methods and apparatus may comprise an integrated circuit comprising a sensor circuit and a driver circuit coupled to the sensor circuit. The driver circuit may include an amplifier configured to generate a bias voltage, a signal converter circuit coupled to the amplifier, and a control circuit coupled to the amplifier. The control circuit may comprise a switch responsive to a control signal and a transistor coupled to the switch.

Claims (107)

1. An integrated circuit, comprising:

a sensor circuit; and

a driver circuit coupled to the sensor circuit and comprising:

an amplifier configured to generate a bias voltage at a bias output terminal;

a signal converter circuit coupled to the amplifier, wherein the signal converter circuit comprises a digital-to-analog converter; and

a control circuit coupled to the amplifier and configured to selectively operate the driver circuit in one of:

a current mode; and

a voltage mode.

2. The integrated circuit according to claim 1 , wherein the control circuit comprises:

a plurality of switches, each responsive to a control signal; and

at least one transistor coupled to at least one of the plurality of switches.

3. The integrated circuit according to claim 1 , wherein the control circuit comprises:

a first switch coupled:

in series with a second switch; and

to the bias output terminal;

a third transistor comprising a gate terminal, wherein the gate terminal is coupled to a node positioned between the first and second switches; and

a third switch and a resistive element coupled between a reference voltage and the amplifier.

4. The integrated circuit according to claim 1 , wherein the sensor circuit comprises a hall element configured to generate a hall signal in response to a magnetic field.

5. The integrated circuit according to claim 1 , further comprising a switching circuit coupled to the sensor circuit and the driver circuit and responsive to a control signal.

6. The integrated circuit according to claim 1 , wherein:

the signal converter circuit is coupled to an inverting terminal of the amplifier; and

the control circuit is coupled to:

a non-inverting terminal of the amplifier; and

a bias output terminal of the amplifier.

7. The integrated circuit according to claim 1 , further comprising:

a first amplifier circuit coupled to an output of the sensor circuit;

a second amplifier circuit coupled to an output of the first amplifier circuit and the driver circuit; and

a switching circuit coupled:

between the first and second amplifier circuits; and

to the driver circuit;

wherein the switching circuit comprises a plurality of switches.

8. The integrated circuit according to claim 7 , wherein the switching circuit comprises:

a fourth switch coupled between a first output terminal of the first amplifier circuit and a first terminal of the second amplifier circuit; and

a fifth switch coupled between a second output terminal of the first amplifier circuit and a second terminal of the second amplifier circuit.

9. The integrated circuit according to claim 8 , wherein the switching circuit further comprises:

a sixth switch coupled between the fourth switch and the driver circuit; and

a seventh switch coupled to:

the fifth switch;

the driver circuit; and

the first input terminal of the first amplifier circuit.

10. A method for operating a hall sensor integrated circuit, comprising:

generating a current with a driver circuit, comprising:

a signal converter comprising a digital-to-analog converter;

an amplifier coupled to the signal converter; and

a control circuit coupled to the amplifier;

generating a sensor signal with the hall sensor;

decoupling a first amplifier circuit from a second amplifier circuit;

generating a voltage with the driver circuit; and

coupling the first amplifier circuit to the second amplifier circuit.

11. The method according to claim 10 , further comprising generating a bias voltage with the amplifier.

12. The method according to claim 11 , wherein:

generating the voltage comprises coupling the control circuit to the bias voltage; and

generating the current comprises decoupling the control circuit from the bias voltage.

13. The method according to claim 10 , further comprising:

sampling the sensor signal with a sampling circuit;

amplifying the sampled sensor signal with the first amplifier circuit; and

amplifying a signal from the first amplifier circuit with the second amplifier circuit.

14. A hall sensor integrated circuit, comprising:

a hall sensor circuit configured to generate a hall signal in response to a magnetic field;

a driver circuit coupled to the hall sensor circuit and configured to operate in one of:

a current mode; and

a voltage mode;

wherein the driver circuit comprises:

a control circuit coupled to a bias voltage;

a first amplifier circuit coupled to an output of the hall sensor circuit;

a second amplifier circuit coupled to the driver circuit; and

a switching circuit coupled between an output of the first amplifier circuit and an input of the second amplifier circuit, comprising:

a plurality of switches, wherein each switch is responsive to a dedicated control signal.

15. The hall sensor integrated circuit according to claim 14 , wherein the driver circuit further comprises:

a signal converter; and

an amplifier coupled to the signal converter, comprising:

an inverting input terminal;

a non-inverting input terminal; and

a bias output terminal;

wherein the amplifier is configured to generate the bias voltage.

16. The hall sensor integrated circuit according to claim 14 , wherein the control circuit further comprises:

a first switch coupled to the bias voltage;

a second switch coupled in series with the first switch;

a third transistor comprising a gate terminal, wherein the gate terminal is coupled to a node positioned between the first and second switches; and

a third switch and a resistive element coupled between a reference voltage and the amplifier;

wherein each of the first, second, and third switches are responsive to a dedicated control signal.

17. The hall sensor integrated circuit according to claim 14 , wherein the switching circuit comprises:

a fourth switch coupled between a first output terminal of the first amplifier circuit and a first terminal of the second amplifier circuit; and

a fifth switch coupled between a second output terminal of the first amplifier circuit and a second terminal of the second amplifier circuit.

18. The hall sensor integrated circuit according to claim 17 , wherein the switching circuit further comprises:

a sixth switch coupled to:

the fourth switch;

the driver circuit; and

the first input terminal of the second amplifier circuit; and

a seventh switch coupled to:

the fifth switch;

the driver circuit; and

the second input terminal of the second amplifier circuit.

19. The hall sensor integrated circuit according to claim 14 , wherein the driver circuit further comprises a current mirror coupled to:

the hall sensor circuit; and

the amplifier.

20. The hall sensor integrated circuit according to claim 14 , further comprising:

a signal converter circuit; and

an amplifier comprising:

an inverting input terminal;

a non-inverting input terminal; and

a bias output terminal;

wherein:

the signal converter circuit is coupled to the inverting terminal of the amplifier; and

the control circuit is coupled to:

the non-inverting terminal of the amplifier; and

the bias output terminal of the amplifier.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2017
From: MURATA, TSUTOMU
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043462/0522 →