Array substrate, display panel and display device
An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.
1. An array substrate, comprising:
a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate;
a semiconductor layer disposed on the substrate;
a fourth insulator layer disposed on the semiconductor layer;
a gate layer disposed on the fourth insulator layer;
a gate insulator layer disposed on the gate layer;
a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and
a third insulator layer disposed on the data line layer,
wherein the common electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the pixel electrode layer are successively disposed on the third insulator layer;
wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line;
wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer; and
wherein the signal transmission line is electrically connected with the common electrode layer.
2. The array substrate according to claim 1 , wherein the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the second insulator layer, the first insulator layer and the third insulator layer, wherein a second via hole is disposed in the first insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole.
3. An array substrate, comprising:
a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate;
a gate layer disposed on the substrate;
a gate insulator layer disposed on the gate layer;
a semiconductor layer disposed on the gate insulator layer;
a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and
a third insulator layer disposed on the data line layer;
wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line;
wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer;
wherein the signal transmission line is electrically connected with the common electrode layer; and
wherein the pixel electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the common electrode layer are successively disposed on the third insulator layer.
4. The array substrate according to claim 3 , wherein, the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the third insulator layer, wherein a second via hole is disposed in the second insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole.
5. An array substrate, comprising:
a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate;
a semiconductor layer disposed on the substrate;
a fourth insulator layer disposed on the semiconductor layer;
a gate layer disposed on the fourth insulator layer;
a gate insulator layer disposed on the gate layer;
a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and
a third insulator layer disposed on the data line layer;
wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line;
wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer;
wherein the signal transmission line is electrically connected with the common electrode layer; and
wherein the pixel electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the common electrode layer are successively disposed on the third insulator layer.
6. The array substrate according to claim 5 , wherein, the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the third insulator layer, wherein a second via hole is disposed in the second insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole.