Biasing current regularization loop stabilization

1. An integrated circuit comprising:

a first stage configured to receive a bias current;

a current regulation loop comprising a transimpedance amplifier that comprises a first transistor, and a second transistor having a gate coupled to a gate of the first transistor, the first transistor and the second transistor configured to compare the bias current with a reference current, and generate a regulation voltage on an output node of the transimpedance amplifier; and

a capacitor coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors, wherein the first stage comprises a radiofrequency (RF) amplifier having a working frequency of greater than 1 gigahertz, the RF amplifier comprising a low-noise amplifier (LNA) that comprises an amplification transistor having a gate coupled to the output node of the transimpedance amplifier via a first resistor.

2. The integrated circuit of claim 1 , wherein the capacitor has a capacitance that is less than 5 picofarads.

3. The integrated circuit of claim 1 , wherein the bias current is configured to have a bandwidth that is lower by at least a factor of ten than a working frequency of the first stage.

4. An integrated circuit comprising:

a first stage configured to receive a bias current;

a current regulation loop comprising a transimpedance amplifier that comprises a first transistor, and a second transistor having a gate coupled to a gate of the first transistor, the first transistor and the second transistor configured to compare the bias current with a reference current, and generate a regulation voltage on an output node of the transimpedance amplifier; and

a capacitor coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors, wherein the first stage comprises a radiofrequency (RF) amplifier having a working frequency of greater than 1 gigahertz, wherein the RF amplifier comprises an NMOS-PMOS dual amplifier comprising a first and second amplification transistors; and wherein a gate of the first amplification transistor is coupled to the output node of the transimpedance amplifier via a second resistor.

5. The integrated circuit of claim 1 , wherein:

the gates of the first and second transistors are coupled to a drain of the second transistor;

the first and second transistors being configured to pass the reference current; and

the output node of the transimpedance amplifier is coupled to a drain of the first transistor.

6. The integrated circuit of claim 1 , wherein the transimpedance amplifier comprises:

a reference current source; and

a current mirror configured to pass copies of the reference current to drains of the first and second transistors.

7. The integrated circuit of claim 1 , wherein the current regulation loop comprises:

a third resistor coupled between a supply terminal configured to receive a supply voltage and a source of the first transistor; and

a fourth resistor coupled between the supply terminal and a source of the second transistor.

8. A circuit comprising:

a first transistor having a first load path node coupled to a first supply terminal;

a second transistor having a first load path node coupled to the first supply terminal, a gate coupled to a gate of the first transistor, and a second load path node coupled to the first load path node of the second transistor;

a first resistor coupled between the first load path node of the first transistor and the first supply terminal;

a second resistor coupled between the first load path node of the second transistor and the first supply terminal;

a first capacitor coupled between a second load path terminal of the first transistor and the gate of the second transistor;

a third transistor having a load path coupled between the second load path node of the first transistor and a second supply terminal;

a fourth transistor having a load path coupled between the second load path node of the second transistor and the second supply terminal, and a gate coupled to a gate of the third transistor;

a third resistor having a first terminal coupled to the second load path node of the first transistor;

a sixth transistor having a gate coupled to a second terminal of the third resistor, a first load path node coupled to the first load path node of the first transistor via an inductive element, and a second load path node coupled to the second supply terminal; and

a second capacitor coupled between the second load path node of the first transistor and the first supply terminal.

9. The circuit of claim 8 , wherein:

the first supply terminal is configured to receive a voltage higher than the second supply terminal, and

the second supply terminal is coupled to a ground reference.

10. The circuit of claim 8 , wherein:

the first transistor is a p-type transistor;

the second transistor is a p-type transistor;

the third transistor is an n-type transistor; and

the fourth transistor is an n-type transistor.

11. The circuit of claim 8 , further comprising a fifth transistor having a load path coupled between the first supply terminal and the second supply terminal, and a gate couple to the gate of the fourth transistor.

12. The circuit of claim 11 , further comprising a current source coupled between the first supply terminal and the load path of the fifth transistor.

13. The circuit of claim 8 , wherein:

the gate of the sixth transistor is configured to receive a first radiofrequency (RF) signal via a third capacitor; and

the first load path node of the sixth transistor is configured to produce a second RF signal based on the first RF signal.

14. The circuit of claim 8 , further comprising the inductive element.

15. A circuit comprising:

a first transistor having a first load path node coupled to a first supply terminal;

a second transistor having a first load path node coupled to the first supply terminal, a gate coupled to a gate of the first transistor, and a second load path node coupled to the first load path node of the second transistor;

a first resistor coupled between the first load path node of the first transistor and the first supply terminal;

a second resistor coupled between the first load path node of the second transistor and the first supply terminal;

a first capacitor coupled between a second load path terminal of the first transistor and the gate of the second transistor;

a third transistor having a load path coupled between the second load path node of the first transistor and a second supply terminal;

a fourth transistor having a load path coupled between the second load path node of the second transistor and the second supply terminal, and a gate coupled to a gate of the third transistor;

a third resistor having a first terminal coupled to the second load path node of the first transistor

a seventh transistor having a gate coupled to a second terminal of the third resistor, and a load path coupled between an output terminal and the second supply terminal;

an eighth transistor having a load path coupled between the first resistor and the load path of the seventh transistor;

a fourth capacitor coupled between a gate of the eighth transistor and an input terminal; and

a fifth capacitor coupled between the input terminal and the gate of the seventh transistor.

16. A method comprising:

receiving a reference current with a transimpedance amplifier comprising a first transistor and a second transistor, the first transistor having a gate coupled to a gate of the second transistor, and a drain of the first transistor being coupled to the gate of the second transistor via a first capacitor;

comparing the reference current with a bias current using the first and second transistors, the bias current configured to pass through a first circuit, the first circuit comprising a third transistor having a gate coupled to a first resistor;

generating a regulation voltage on an output node of the transimpedance amplifier, the output node of the transimpedance amplifier coupled to the first resistor;

receiving a first radiofrequency (RF) signal in the gate of the third transistor; and

generating a second RF signal in an output terminal based on the first RF signal.

17. The method of claim 16 , wherein the bias current flows through an inductor coupled in series with a load path of the third transistor, the inductor coupled to a second capacitor.

18. A method comprising:

receiving a reference current with a transimpedance amplifier comprising a first transistor and a second transistor, the first transistor having a gate coupled to a gate of the second transistor, and a drain of the first transistor being coupled to the gate of the second transistor via a first capacitor;

comparing the reference current with a bias current using the first and second transistors, the bias current configured to pass through a first circuit, the first circuit comprising a radiofrequency (RF) amplifier having a working frequency of greater than 1 gigahertz, the RF amplifier comprising an NMOS-PMOS dual amplifier that comprises a third transistor having a gate coupled to a first resistor and a fourth transistor; and

generating a regulation voltage on an output node of the transimpedance amplifier, the output node of the transimpedance amplifier coupled to the first resistor, wherein the reference current flows through a load path of the fourth transistor; and

copying the reference current using a current mirror comprising a fifth transistor and a sixth transistor, the fifth transistor coupled between the first transistor and a reference terminal, and the sixth transistor coupled between the second transistor and the reference terminal.

19. The method of claim 18 , wherein generating the regulation voltage on the output node of the transimpedance amplifier comprises generating the regulation voltage on the output node of the transimpedance amplifier without having a capacitor connected between the output node of the transimpedance amplifier and the reference terminal.

20. The integrated circuit of claim 1 , wherein the current regulation loop is configured to generate the regulation voltage on the output node of the transimpedance amplifier without having a capacitor connected to the output node of the transimpedance amplifier.

21. The integrated circuit of claim 4 , wherein the bias current is configured to have a bandwidth that is lower by at least a factor of ten than a working frequency of the first stage.

22. The integrated circuit of claim 4 , wherein the capacitor has a capacitance that is less than 5 picofarads.