Dynamic triggering and sampling engine (DTSE) for low-latency and cost effective control systems
A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.
1. An integrated circuit, comprising:
a hardware trigger input;
a memory that stores a trigger mapping table and a sequence configuration table; and
a state machine, wherein the state machine is configured to:
detect a trigger received on the hardware trigger input, wherein the trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit, wherein the analog-to-digital conversions include critical samples and non-critical samples;
determine a sequence configuration stored in the sequence configuration table that is associated with the trigger; and
cause one of the analog-to-digital conversions to be performed using the sequence configuration, wherein at least one of the critical samples is performed before at least one of the non-critical samples.
2. The integrated circuit of claim 1 , wherein the state machine is also configured to output an interrupt indicating that the analog-to-digital conversion has been completed by the analog-to-digital circuit.
3. The integrated circuit of claim 2 , wherein the interrupt is output before at least one of the remaining analog-to-digital conversions in the series is completed.
4. The integrated circuit of claim 2 , wherein the interrupt is output after at least one of the critical samples of the series of analog-to-digital conversions is completed.
5. The integrated circuit of claim 2 , wherein the interrupt is output after at least one of the non-critical samples of the series of analog-to-digital conversions is completed.
6. The integrated circuit of claim 1 , wherein the memory also stores a sequence result table.
7. The integrated circuit of claim 6 , wherein the state machine is also configured to cause a analog-to-digital conversion result value to be stored in the sequence result table.
8. The integrated circuit of claim 6 , wherein each sequence configuration stored in memory is associated with a unique entry in the sequence result table.
9. The integrated circuit of claim 1 , wherein the trigger mapping table is programmed by another device via a bus terminal.
10. The integrated circuit of claim 9 , wherein the bus is an Advanced Microcontroller Bus Architecture (AMBA) bus.
11. The integrated circuit of claim 1 , wherein the integrated circuit is configurable to detect a rising edge of a Pulse Width Modulate (PWM) signal on the hardware trigger input or a Pulse Width Modulate (PWM) signal on the hardware trigger input.
12. The integrated circuit of claim 1 , wherein the state machine is implemented using a microcontroller.
13. The integrated circuit of claim 1 , wherein the state machine is implemented using combinatory logic.
14. The integrated circuit of claim 1 , wherein the integrated circuit includes a plurality of hardware trigger inputs.
15. The integrated circuit of claim 1 , wherein the memory comprises a plurality of storage devices.
16. A method, comprising:
(a) detecting a trigger received on a hardware trigger input, wherein the trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit, and wherein the series of analog-to-digital conversions includes critical conversions and non-critical conversions;
(b) determining a sequence configuration stored in a sequence configuration table that is associated with the trigger;
(c) causing an analog-to-digital conversion to be performed using the sequence configuration;
(d) causing an analog-to-digital conversion result value to be stored in a sequence result table; and
(e) outputting an interrupt indicating that the analog-to-digital conversion result value is available in the sequence result table, wherein the interrupt is output before at least one of the non-critical conversions in the series is completed.
17. The method of claim 16 , wherein (a) through (e) are performed by a state machine in a Dynamic Triggering and Sample Engine (DTSE).
18. An apparatus comprising:
a hardware trigger input; and
means for detecting a trigger received on the hardware trigger input, wherein the trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit, wherein the analog-to-digital conversions include critical samples and non-critical samples, wherein the means is also for causing at least one of the critical samples to be performed before at least one of the non-critical samples.
19. The apparatus of claim 18 , wherein the means is a state machine of a Dynamic Triggering and Sample Engine (DTSE).
20. The apparatus of claim 18 , wherein the means is also for determining a sequence configuration stored in a sequence configuration table that is associated with the trigger, and wherein the means is also for outputting an interrupt indicating that an analog-to-digital conversion has been completed by the analog-to-digital circuit.