Multi-segmented all logic DAC
A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.
1. A digital-to-analog converter (DAC), comprising:
a plurality of segments, wherein the plurality of segments includes
a first segment communicably coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB),
a second segment communicably coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and
a third segment communicably coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs, the second number of LSBs in the third segment being configured in an R-2R ladder structure.
2. The DAC of claim 1 , wherein the DAC includes an all logic implementation, wherein the all logic implementation include one or more of CMOS gates, PMOS gates, or NMOS gates.
3. The DAC of claim 1 , wherein the first segment is thermometer encoded based on the predetermined number of MSBs.
4. The DAC of claim 1 , wherein the first predetermined number of LSBs in the second segment are binary encoded parallel matched LSBs.
5. The DAC of claim 1 , wherein the second segment is positioned between the first segment and the third segment.
6. The DAC of claim 1 , wherein the third segment includes one or more capacitors placed across the R-2R ladder structure.
7. The DAC of claim 1 , wherein the DAC includes a predetermined number of bits, wherein the predetermined number of MSBs, the first predetermined number of LSBs, and the second predetermined number of LSBs add up to the predetermined number of bits of the DAC.
8. The DAC of claim 7 , wherein each of the predetermined number of MSBs, the first predetermined number of LSBs, and the second predetermined number of LSBs are determined based on a performance optimization of the DAC for an application for which the DAC is being used.
9. The DAC of claim 8 , wherein the performance optimization is determined based on a tradeoff between linearity, area, speed, and power.
10. An electronic circuit, comprising:
a first segment configured to receive digital input;
a second segment coupled to the first segment, wherein the second segment is configured to receive the digital input;
a third segment couple to the second segment, wherein the third segment is configured to receive the digital input; and
wherein each of first segment, the second segment, and the third segment includes
one or more resistors, and
one or more complementary metal-oxide-semiconductor (CMOS) gates coupled to each of the one or more resistors, and
the third segment includes a second predetermined number of least significant bits (LSBs) configured in an R-2R ladder structure.
11. The electronic circuit of claim 10 , wherein a combination of each of the first segment, the second segment, and the third segment is configured to convert the digital input to analog output.
12. The electronic circuit of claim 10 , wherein the first segment includes a predetermined number of most significant bits (MSB).
13. The electronic circuit of claim 10 , wherein the second segment includes a first predetermined number of least significant bits (LSB).
14. The electronic circuit of claim 12 , wherein the first segment is thermometer encoded based on the predetermined number of MSBs.
15. The electronic circuit of claim 13 , wherein the first predetermined number of LSBs in the second segment is binary encoded parallel matched LSBs.
16. The electronic circuit of claim 10 , the third segment includes one or more capacitors placed across the R-2R ladder structure.
17. The electronic circuit of claim 10 , wherein a number of the one or more resistors and corresponding CMOS gates for each resistor for each of the first segment, the second segment, and the third segment is based on a performance optimization of the digital-to-analog conversion for an application for which the electronic circuit is being used.