Integrated device with P-I-N diodes and vertical field effect transistors

1. An integrated device, comprising:

a substrate having a doped upper surface section with an uppermost surface, an un-doped layer underlying the doped upper surface section and an insulator extending downwardly from the uppermost surface, through the doped upper surface section and into the un-doped layer to define first and second substrate regions on opposite sides thereof;

vertical transistors operably arranged on the doped upper surface section at the first substrate region; and

P-I-N diodes operably arranged on the doped upper surface section at the second substrate region.

2. The integrated device according to claim 1 , wherein the vertical transistors comprise vertical field effect transistors (VFETs) and the insulator comprises a shallow trench insulator.

3. The integrated device according to claim 1 , wherein:

the doped upper surface section comprises N+ doping at a first sub-region of the first substrate region and P+ doping at a second sub-region of the first substrate region,

a first sub-group of the vertical transistors associated with the first sub-region comprises N+ source and drain contacts, and

a second sub-group of the vertical transistors associated with the second sub-region comprises P+ source and drain contacts.

4. The integrated device according to claim 1 , further comprising:

an intrinsic layer disposed on the doped upper surface section at the second substrate region; and

a doped layer disposed over each one of the P-I-N diodes at the second substrate region.

5. The integrated device according to claim 4 , wherein the doped upper surface section and the doped layer respectively comprise complementary doping.

6. The integrated device according to claim 4 , wherein the doped layer is merged between adjacent ones of the P-I-N diodes.

7. The integrated device according to claim 1 , further comprising:

interlayer dielectric (ILD) disposed around and over the vertical transistors and the P-I-N diodes;

at least one first conductor extending through the ILD to the doped upper surface section;

at least one second conductor extending through the ILD to at least a corresponding one of the vertical transistors; and

at least one third conductor extending through the ILD to at least a corresponding one of the P-I-N diodes.

8. A method of forming an integrated device, comprising:

doping an upper surface section with an uppermost surface of a substrate;

forming an insulator to extend downwardly into the substrate from the uppermost surface, through the doped upper surface section and into an un-doped layer underlying the doped upper surface section to define first and second substrate regions on opposite sides thereof;

operably arranging vertical transistors for disposition on the doped upper surface section at the first substrate region; and

operably arranging P-I-N diodes for disposition on the doped upper surface section at the second substrate region.

9. The method according to claim 8 , wherein the vertical transistors comprise vertical field effect transistors (VFETs) and the insulator comprises a shallow trench insulator.

10. The method according to claim 8 , wherein the doping of the upper surface section comprises:

N+ doping at a first sub-region of the first substrate region; and

P+ doping at a second sub-region of the first substrate region.

11. The method according to claim 10 , wherein the operably arranging of the vertical transistors comprises:

forming N+ source and drain contacts for a first sub-group of the vertical transistors associated with the first sub-region; and

forming P+ source and drain contacts for a second sub-group of the vertical transistors associated with the second sub-region.

12. The method according to claim 8 , further comprising:

disposing an intrinsic layer on the doped upper surface section at the second substrate region; and

disposing a doped layer over each one of the plurality of P-I-N diodes at the second substrate region.

13. The method according to claim 12 , wherein the doped upper surface section and the doped layer respectively comprise complementary doping.

14. The method according to claim 12 , further comprising merging the doped layer between adjacent ones of the plurality of P-I-N diodes.

15. The method according to claim 8 , further comprising:

disposing interlayer dielectric (ILD) around and over the vertical transistors and the P-I-N diodes;

forming at least one first conductor to extend through the ILD to the doped upper surface section;

forming at least one second conductor to extend through the ILD to at least a corresponding one of the vertical transistors; and

forming at least one third conductor to extend through the ILD to at least a corresponding one of the P-I-N diodes.

16. A method of forming an integrated device on a semiconductor substrate having an uppermost surface, the method comprising:

insulating vertical transistor and diode regions of the semiconductor substrate;

forming fin structures in the transistor region;

forming pillar structures in the diode regions;

doping an upper surface section of the semiconductor substrate to define an un-doped layer underlying the doped upper surface section, wherein the insulating extends downwardly from the uppermost surface, through the doped upper surface section and into the un-doped layer;

changing the fin structures into vertical field effect transistors (VFETs) in the vertical transistor region and changing the pillar structures into P-I-N diodes in the diode region; and

patterning contacts for electrical coupling with the doped upper surface section, at least one of the VFETs and at least one of the P-I-N diodes.

17. The method according to claim 16 , wherein the changing of the fin structures into the VFETs in the vertical transistor region and the changing of the pillar structures into the P-I-N diodes in the diode region comprises:

masking the vertical transistor region;

stripping spacers and hardmasks in the diode region;

doping the pillar structures in the diode region; and

epitaxially growing intrinsic and doped layers in the diode region.

18. The method according to claim 17 , further comprising merging the doped layer between adjacent ones of the P-I-N diodes.

19. The method according to claim 16 , wherein the vertical transistor region comprises N+ and P+ sub-regions and the sequential modifying comprises one of:

masking the diode and the P+ sub-region, forming high-k metal gates and N+ source and drain contacts in the N+ sub-region and forming high-k metal gates and P+ source and drain contacts in the P+ sub-region; and

masking the diode and the N+ sub-region, forming high-k metal gates and P+ source and drain contacts in the P+ sub-region and forming high-k metal gates and N+ source and drain contacts in the N+ sub-region.