Cross-point offset adjustment circuit
View Patent ↗A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.
1. A differential signal offset adjustment circuit, comprising:
a first circuit for receiving a first one of a differential input signal including a DC offset and generating a first one of a differential output signal with a positive offset based on a combination of a differential offset signal and the DC offset; and
a second circuit for receiving a second one of the differential input signal including the DC offset and generating a second one of the differential output signal with a negative offset based on a combination of the differential offset signal and the DC offset.
2. The differential signal offset adjustment circuit of claim 1 , wherein the first circuit includes:
a first branch including a first transistor coupled between a first current source and a second current source, and
a second branch including a second transistor coupled between a third current source and a fourth current source.
3. The differential signal offset adjustment circuit of claim 2 , further comprising a first resistor coupled between the first one of the differential input signal and the first one of the differential output signal.
4. The differential signal offset adjustment circuit of claim 3 , further comprising a first capacitor in parallel with the first resistor.
5. The differential signal offset adjustment circuit of claim 3 , further comprising a second resistor coupled between the first branch and the second branch.
6. The differential signal offset adjustment circuit of claim 2 , wherein the second circuit includes:
a third branch including a third transistor coupled between a fifth current source and a sixth current source, and
a fourth branch including a fourth transistor coupled between a seventh current source and an eighth current source.
7. The differential signal offset adjustment circuit of claim 6 , further comprising a third resistor coupled between the second one of the differential input signal and the second one of the differential output signal.
8. The differential signal offset adjustment circuit of claim 7 , further comprising a second capacitor in parallel with the third resistor.
9. The differential signal offset adjustment circuit of claim 7 , further comprising a fourth resistor coupled between the third branch and the fourth branch.
10. The differential signal offset adjustment circuit of claim 1 , further comprising a bandwidth enhancement circuit coupled across the differential input signal.
11. A method, comprising:
receiving a first one of a differential input signal including a DC offset at a first circuit;
generating a first one of a differential output signal with a positive offset voltage based on a combination of a differential offset signal and the DC offset;
receiving a second one of the differential input signal including the DC offset at a second circuit; and
generating a second one of the differential output signal with a negative offset voltage based on a combination of the differential offset signal and the DC offset.
12. The method of claim 11 , further comprising:
sourcing a first current plus an offset current through a first transistor in a first branch of the first circuit; and
sourcing a second current minus the offset current through a second transistor in a second branch of the first circuit, the first current and the second current being substantially equal.
13. The method of claim 12 , further comprising:
controlling the first transistor with a first one of the positive and negative offset voltages; and
controlling the second transistor with a second one of the positive and negative offset voltages.
14. The method of claim 12 , further comprising resistively coupling the first one of the differential input signal to the first one of the differential output signal.
15. The method of claim 14 , further comprising capacitively bypassing the resistively coupling of the first branch to the second branch.
16. The method of claim 14 , further comprising resistively coupling the first branch to the second branch.
17. The method of claim 12 , further comprising:
sourcing a third current plus an offset current through a third transistor in a third branch of the second circuit; and
sourcing a fourth current minus the offset current through a fourth transistor in a fourth branch of the second circuit, the third and fourth currents being substantially equal.
18. The method of claim 17 , further comprising:
controlling the third transistor with a first one of the positive and negative offset voltages; and
controlling the fourth transistor with a second one of the positive and negative offset voltages.
19. The method of claim 17 , further comprising resistively coupling the second one of the differential input signal to the second one of the differential output signal.
20. The method of claim 19 , further comprising capacitively bypassing the resistively coupling of the third branch to the fourth branch.