Equalization for transmitter input buffer array
View Patent ↗The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.
1. An input buffer device comprising:
a first input terminal;
a first plurality of inverters comprising n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal;
a first equalization element being characterized by a predetermined resistance value, the predetermined resistance value being based on a delay associated with the first group of m inverters, the first equalization element being configured in series relative to the first group of m inverters;
a first output terminal coupled to the first plurality of inverters;
a second input terminal;
a second plurality of inverters;
a second output terminal coupled to the second plurality of inverters; and
a second equalization element coupled to the second plurality of inverters.
2. The device of claim 1 wherein the first equalization element comprises a resistor.
3. The device of claim 1 wherein the first equalization element comprises a resistor and a switch.
4. The device of claim 3 wherein the switch disables the first equalization element if a control signal indicates no signals on the first input terminal.
5. The device of claim 1 wherein m is an odd integer.
6. The device of claim 1 wherein the first equalization element comprises an inverter.
7. The device of claim 1 wherein the resistance value is between 500 ohms and 5000 ohms.
8. The device of claim 1 wherein the first input terminal and the second input terminal receive differential input signals.
9. A digital-to-analog converter (DAC) system comprising:
a DAC device being configured to convert n bits of input data, n indicating a number of bits;
a first input buffer module comprising a first plurality of inverters and a first equalization element, the first input buffer module being configured to provide a first input signal to the DAC device;
a second input buffer module comprising a second plurality of inverters and a second equalization element, the second input buffer module being configured to provide a second input signal to the DAC device;
wherein:
the first input signal and the second input signal form a pair of differential inputs signals;
the first plurality of inverters includes a first a segment of m inverters, m indicating a quantity of inverters, the first segment of m inverters being associated with a first delay value; and
the first equalization element is characterized by a first predetermined resistance value, the first predetermined resistance value being determined based on the first delay value.
10. The system of claim 9 further comprising n input buffer modules, each of the n input buffer modules corresponding to one of the n bits of input data.
11. The system of claim 10 wherein each of the n input buffer modules provides a pair of differential input signals.
12. The system of claim 9 wherein the m is an odd integer.
13. The system of claim 9 wherein the first equalization element comprises a resistor.
14. The system of claim 9 wherein the first equalization element comprises a transmission gate and a resistor.
15. The system of claim 9 wherein:
the second plurality of inverters includes a second a segment of m inverters, the second segment of m inverters being associated with a second delay value; and
the second equalization element is characterized by a second predetermined resistance value, the second predetermined resistance value being determined based on the second delay value.
16. A data input buffer device comprising:
a first input terminal;
a first plurality of inverters comprising n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal;
a first output terminal coupled to the first plurality of inverters;
a second input terminal;
a second plurality of inverters comprising n inverters configured in series, the second plurality of inverters including a second inverter and a second group of m inverters, the second inverter being coupled to the second input terminal;
a first equalization element being characterized by a first predetermined resistance value, the first predetermined resistance value being based on a delay associated with the second group of m inverters, the first equalization element being configured in series relative to the second group of m inverters;
a second equalization element being characterized by a second predetermined resistance value, the first predetermined resistance value being based on a delay associated with the first group of m inverters, the second equalization element being configured in series relative to the first group of m inverters; and
a second output terminal coupled to the second plurality of inverters.
17. The device of claim 16 wherein m is an even integer.
18. The device of claim 16 wherein the first equalization element comprises a resistor and a transmission gate.
19. The device of claim 16 wherein the first equalization element comprises an equalization inverter, the equalization inverter being characterized by a resistance value of less than 10,000 ohms.
20. The device of claim 16 wherein the data input buffer device is characterized by an operating frequency of at least 10 Gbps.