IP Library Granted Patent US 10,168,907
Granted Patent B2
US 10,168,907 · App. 15/700,539 · Granted Jan 1, 2019

Memory system and operating method thereof

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Quick Facts
Patent No.
US 10,168,907
App. No.
15/700,539
Granted
Jan 1, 2019
Kind
B2
Abstract

a memory system may include: a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host.

Claims (16)

1. A memory system comprising:

a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host, wherein the request message includes a data array having information on data splits of the target transaction group, and address lists of the target transaction group, wherein the request message further includes a header having a flag indicating type information of the data defragmentation and data remapping operations, wherein the type information indicates at last one among a general mode, a fast mode, an optimized mode, a cold mode and a hot mode.

2. The memory system according to claim 1 , wherein the header further has a total size of the target transaction group.

3. The memory system according to claim 1 , wherein the header further has a split count of the target transaction group.

4. The memory system according to claim 1 , wherein the information on data splits of the target transaction group of the data array has start addresses and address sizes for respective data splits of the target transaction group.

5. The memory system according to claim 1 , wherein the controller identifies a data distribution of the target transaction group in the memory device through the header, the data array and the address lists of the target transaction group.

6. The memory system according to claim 5 , wherein the controller performs the one or more of data defragmentation and data remapping operations for the data splits of the target transaction group with memory blocks of memory dies coupled to the same channel or memory blocks of the same cell type.

7. The memory system according to claim 5 , wherein the controller performs only a data remapping operation for metadata of the data splits of the target transaction group.

8. A method for operating a memory system, comprising:

receiving, from a host, a request message with respect to a memory device including a plurality of memory dies each having a plurality of memory blocks; and performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to the request message, wherein the request message includes a data array having information on data splits of the target transaction group, and address lists of the target transaction group, wherein the request message further includes a header having a flag indicating type information of the data defragmentation and data remapping operations, wherein the type information indicates at last one among a general mode, a fast mode, an optimized mode, a cold mode and a hot mode.

9. The method according to claim 8 , wherein the header further has a total size of the target transaction group.

10. The method according to claim 8 , wherein the header further has a split count of the target transaction group.

11. The method according to claim 8 , wherein the information on data splits of the target transaction group of the data array has start addresses and address sizes for respective data splits of the target transaction group.

12. The method according to claim 8 , wherein the performing includes identifying a data distribution of the target transaction group in the memory device through the header, the data array and the address lists of the target transaction group.

13. The method according to claim 10 , wherein the one or more of data defragmentation and data remapping operations are performed for the data splits of the target transaction group with memory blocks of memory dies coupled to the same channel or memory blocks of the same cell type.

14. The method according to claim 10 , wherein only the data remapping operation is performed for metadata of the data splits of the target transaction group.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2017
From: CHANG, GI-SEOB; SHIN, SOONG-SUN
To: SK HYNIX INC.
Reel/Frame 043544/0805 →