IP Library Granted Patent US 10,256,295
Granted Patent B2
US 10,256,295 · App. 15/704,703 · Granted Apr 9, 2019

Semiconductor device

Inventors: Masahiro Kawakami (Nissin, JP); Tomohiko Mori (Nagakute, JP); Hiroyuki Ueda (Nagakute, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L29/063H01L21/0254H01L21/02576H01L21/26546H01L21/30617H01L21/3245H01L29/1095H01L29/2003H01L29/7395H01L29/7802
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Quick Facts
Patent No.
US 10,256,295
App. No.
15/704,703
Granted
Apr 9, 2019
Kind
B2
Abstract

A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type region, and a gate electrode. The outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region.

Claims (10)

1. A semiconductor device comprising:

an outside-of-well n-type region;

a p-type well region that is surrounded by the outside-of-well n-type region and is exposed to a surface of a semiconductor substrate;

an inside-of-well n-type region that is surrounded by the p-type well region and is exposed to the surface of the semiconductor substrate; and

a gate electrode that is opposed, via an insulating film, to a surface of the p type well region in an area in which the outside-of-well n-type region and the inside-of-well n-type region are separated from each other, wherein

the outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region, the impurity low-concentration region containing a lower concentration of an n-type impurity than the impurity high-concentration region, and

the impurity high-concentration region includes a first portion and a second portion, the first portion having a first thickness in a thickness direction of the semiconductor substrate, the second portion having a second thickness in the thickness direction, the second thickness being larger than the first thickness and the second portion protruding from the first portion towards the surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein an impurity middle-concentration region is provided between the impurity low-concentration region and the impurity high-concentration region.

3. The semiconductor device according to claim 1 , wherein the outside-of-well n-type region comprises an epitaxially grown, nitride semiconductor.

4. The semiconductor device according to claim 1 , wherein the insulating film and the gate electrode extend over a gap between adjacent ones of the p-type well region, and, in the gap, the impurity low-concentration region is in contact with the insulating film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 053727/0319 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2017
From: KAWAKAMI, MASAHIRO; MORI, TOMOHIKO; UEDA, HIROYUKI
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 043865/0385 →
Priority Claims (1)
JP 2016-199498 · Oct 7, 2016 · national
Continuity (1)
Related Publication 20180102405A1 · Apr 12, 2018