Method for performing dual dispatch of blocks and half blocks
A method by a processor for performing multi-dispatch of instruction blocks. The method includes receiving an incoming sequence of instructions, grouping the instructions to form instruction blocks including a first instruction block, and performing a multi-dispatch of the first instruction block for execution on one or more execution units by dispatching the first instruction block multiple times, wherein different instructions within the first instruction block are executed for each dispatch.
1. A method by a processor for performing multi-dispatch of instruction blocks, the method comprising:
receiving an incoming sequence of instructions;
grouping the instructions to form instruction blocks including a first instruction block; and
performing a multi-dispatch of the first instruction block for execution on one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
2. The method of claim 1 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being held in a transient state that is not architecturally visible.
3. The method of claim 1 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being architecturally visible.
4. The method of claim 1 , wherein the first instruction block is allocated, committed, and retired as a single entity.
5. The method of claim 1 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for executing a load address instruction and a second dispatch of the multi-dispatch is for executing a load data instruction.
6. The method of claim 1 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for performing a fixed point multiply and the second dispatch of the multi-dispatch is for performing a floating point addition and rounding.
7. A processor comprising:
a fetch unit to receive an incoming sequence of instructions;
a scheduler to group the instructions to form instruction blocks including a first instruction block;
one or more execution units to execute instructions; and
a dispatcher to perform a multi-dispatch of the first instruction block for execution on the one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
8. The processor of claim 7 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being held in a transient state that is not architecturally visible.
9. The processor of claim 7 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being architecturally visible.
10. The processor of claim 7 , further comprising circuitry to allocate, commit, and retire the first instruction block as a single entity.
11. The processor of claim 7 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for executing a load address instruction and a second dispatch of the multi-dispatch is for executing a load data instruction.
12. The processor of claim 7 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for performing a fixed point multiply and the second dispatch of the multi-dispatch is for performing a floating point addition and rounding.
13. A computer system comprising:
a memory; and
a processor comprising
a fetch unit to receive an incoming sequence of instructions,
a scheduler to group the instructions to form instruction blocks including a first instruction block,
one or more execution units to execute instructions, and
a dispatcher to perform a multi-dispatch of the first instruction block for execution on the one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
14. The processor of claim 13 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being held in a transient state that is not architecturally visible.
15. The processor of claim 13 , wherein performing the multi-dispatch includes dispatching the first instruction block with its intermediate result being architecturally visible.
16. The processor of claim 13 , wherein the processor further comprises circuitry to allocate, commit, and retire the first instruction block as a single entity.
17. The processor of claim 13 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for executing a load address instruction and a second dispatch of the multi-dispatch is for executing a load data instruction.
18. The processor of claim 13 , wherein the multi-dispatch includes a first dispatch and a second dispatch, and wherein the first dispatch of the multi-dispatch is for performing a fixed point multiply and the second dispatch of the multi-dispatch is for performing a floating point addition and rounding.